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OR2C04A

ORCA® Series 2 Field-Programmable Gate Arrays

Lattice Semiconductor 

Data Sheet

January 2002

ORCA Series 2 FPGAs

Index

A

Absolute Maximum Ratings, 129

Adder (see LUT Operating Modes)

Architecture

Overview, 5

PLC, 22

PIC, 25

B

Bidirectional Buffers (BIDIs), 14, 17, 18, 20, 22

(see also Routing and SLIC)

Bit Stream (see FPGA Configuration)

Bit Stream Error Checking, 47

(see also FPGA States of Operation)

Boundary Scan, 54—59

C

Clock Distribution Network, 37—39

Selecting Clock Input Pins, 39

Clock Enable (CE), 1, 5, 7, 15, 16, 24, 134

Comparator (see LUT Operating Modes)

Configuration (see FPGA States of Operation

or FPGA Configuration)

Control Inputs, 5, 7

E

Electrical Characteristics, 130

Error Checking (see FPGA Configuration)

F

5 V Tolerant I/O, 26—27, 64

FPGA Configuration

Configuration Frame Format, 43—46

Configuration Modes, 47, 158—160

Asynchronous Peripheral Mode, 49, 163

Daisy-Chaining, 51

Master Parallel Mode, 47

Master Serial Mode, 162

Slave Parallel Mode, 48, 50, 161, 166

Slave Serial Mode, 49—50, 165

Synchronous Peripheral Mode, 48, 164

Data Format, 43—45

Using ORCA Foundry to Generate RAM Data, 43

FPGA States of Operation, 40—43

Configuration, 41

Initialization, 40

Other Configuration Options, 43

Partial Reconfiguration, 43

Reconfiguration, 42

Start-Up, 41

G

GSR (see GSRN)

GSRN, 6, 7, 16, 37, 134

I

IEEE Standard 1149.1, 1

(see also Boundary Scan)

Initialization (see FPGA States of Operation)

Input/Output Buffers (see PICs)

Measurement Conditions, 169

Output Buffer Characteristics, 170—172

J

JTAG (see Boundary Scan)

L

Look-up Table (LUT) Operating Modes, 7—15

Adder-Subtractor Submode, 10

Counter Submode, 11

Equality Comparators, 11

Logic Modes, 7—9

Memory Mode, 12—15

Asynchronous Memory, 12

Synchronous Memory, 13

Multiplier Submode, 11

Ripple Mode, 10

LSR, 5—7, 15—16

M

Maximum Ratings (see Absolute Maximum Ratings)

Multiplier (see LUT Operating Modes)

O

ORCA Foundry Development System Overview, 4

Ordering Information, 189

Package Matrix, 190

Package Options, 189

Temperature Options, 189

Voltage Options, 189

Output (see PICs)

P

Package Outline Drawings, 174—186

Package Matrix, 190

Package Outline Drawings, 173

84-Pin PLCC, 174

100-Pin TQFP, 175

144-Pin TQFP, 176

Lattice Semiconductor

189

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