MX28F1000P Ver la hoja de datos (PDF) - Unspecified

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MX28F1000P

1M-BIT [128K x 8] CMOS FLASH MEMORY

Unspecified 

MX28F1000P

AUTOMATIC BLOCK ERASE TIMING WAVEFORM

Block data indicated by A12 to A16 are erased. External

erase verify is not required because data are erased

automatically by internal control circuit. Erasure comple-

tion can be verified by DATA polling and toggle bit

checking after automatic erase starts. Device outputs 0

during erasure and 1 after erasure on Q7. Q0 to Q5 (Q6

is for toggle bit; see toggle bit, DATA polling, timing

waveform) are in high impedance.

Vcc 5V

12V

Vpp

0V

A0 ~ A11

A12 ~ A16

CE

WE

OE

Q7

Q0~Q5

Setup auto block erase/erase command

tVPS

Block

Block

address 0 address 1

tCH

tCS

tAS

tCWC

tAH

tBALC

tCEPH1

tOES tCEP

tCEP tCEPH2

tDS tDH tDS tDH

Command in Command in

Command in Command in

Command #20H Command #D0H

*Refer to page 2 for detailed block address.

Auto block erase & DATA polling

tVPH

Block

address #

tBAL

tAETB

tAH1

tCESC

tDF

tDPA

DATA polling

P/N: PM0340

REV. 1.6, JAN. 19, 1999

20

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