MX26L6420XBC-90 Ver la hoja de datos (PDF) - Macronix International

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MX26L6420XBC-90

64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM

Macronix International 

MX26L6420

ACCELERATED PROGRAM OPERATIONS

The device offers accelerated program operations through

the ACC pin. When the system asserts VHH on the ACC

pin, the device automatically bypass the two "Unlock"

write cycle. The device uses the higher voltage on the

ACC pin to accelerate the operation. Note that the ACC

pin must not be at VHH any operation other than accelerated

programming, or device damage may result.

SETUP AUTOMATIC CHIP ERASE

Chip erase is a six-bus cycle operation. There are two

"unlock" write cycles. These are followed by writing the

"set-up" command 80H. Two more "unlock" write cycles

are then followed by the chip erase command 10H.

The MX26L6420 contains a Silicon-ID-Read operation to

supplement traditional PROM programming methodology.

The operation is initiated by writing the read silicon ID

command sequence into the command register. Follow-

ing the command write, a read cycle with A6=VIL,

A1=VIL, A0=VIL retrieves the manufacturer code of C2H.

A read cycle with A6=VIL, A1=VIL, A0=VIH returns the

device code of 22FCH for MX26L6420.

AUTOMATIC CHIP ERASE COMMAND

The device does not require the system to preprogram

prior to erase. The Automatic Erase algorithm automati-

cally preprograms and verifies the entire memory for an

all zero data pattern prior to electrical erase.The system

is not required to provide any controls or timings during

these operations. Table 4 shows the address and data

requirements for the chip erase command sequence.

Any commands written to the chip during the Automatic

Erase algorithm are ignored. Note that a hardware reset

during the chip erase operation immediately terminates

the operation. The Chip Erase command sequence should

be reinitiated once the device has returned to reading

array data, to ensure data integrity.

The system can determine the status of the erase op-

eration by using Q7, Q6. See "Write Operation Status"

for information on these status bits. When the Automatic

Erase algorithm is complete, the device returns to read-

ing array data and addresses are no longer latched.

Figure 5 illustrates the algorithm for the erase opera-

tion.See the Erase/Program Operations tables in "AC

Characteristics" for parameters, and to Figure 4 for tim-

ing diagrams.

TABLE 5. SILICON ID CODE

Pins

A0 A1 A6 Q15 Q7 Q6

|

Q8

Manufacture code

VIL VIL VIL 00H 1 1

Device code for MX26L6420 VIH VIL VIL 22H 1 1

Q5 Q4 Q3 Q2 Q1 Q0 Code(Hex)

0 0 0 0 1 0 00C2H

1 1 1 1 1 0 22FCH

P/N:PM0823

REV. 0.5, JAN. 29, 2002

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