MX25L12805D Ver la hoja de datos (PDF) - Unspecified

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MX25L12805D

128M-BIT [x 1] CMOS SERIAL FLASH

Unspecified 

MX25L12805D

DEVICE OPERATION

1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation.

2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until

next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.

3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next

CS# rising edge.

4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK. The

difference of Serial mode 0 and mode 3 is shown as Figure 3.

5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, RES and REMS the shifted-in instruction

sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the

following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, RDP, DP, ENSO, EXSO,and WRSCUR, the CS# must

go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.

6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and

not affect the current operation of Write Status Register, Program, Erase.

Figure 3. Serial Modes Supported

CPOL CPHA

(Serial mode 0) 0

0 SCLK

(Serial mode 3) 1

1 SCLK

SI

SO

MSB

MSB

Note:

CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not

transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is

supported.

P/N: PM1310

REV. 1.1, OCT. 01, 2008

11

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