MU9C3480A Ver la hoja de datos (PDF) - MUSIC Semiconductors
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MU9C3480A Datasheet PDF : 32 Pages
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LANCAM A/L series (not recommended for new designs)
Instruction Set Summary
INSTRUCTION SET SUMMARY
Mnemonic Format: INS dst, src[msk], val
INS: Instruction mnemonic
dst: Destination of the data
src: Source of the data
msk: Mask register used
val: Validity condition set at the location written
Instruction: Select Persistent Source
Operation
Comparand Register
Mask Register 1
Mask Register 2
Memory Array at Addr. Reg.
Memory Array at Address
Mem. at Highest-Priority Match
Mnemonic
SPS CR
SPS MR1
SPS MR2
SPS M@[AR]
SPS M@aaaH
SPS M@HM
Op-Code
0000H
0001H
0002H
0004H
0804H
0005H
Instruction: Select Persistent Destination
Operation
Comparand Register
Masked by MR1
Masked by MR2
Mask Register 1
Mask Register 2
Mem. at Addr. Reg. set Valid
Masked by MR1
Masked by MR2
Mem. at Addr. Reg. set Empty
Masked by MR1
Masked by MR2
Mem. at Addr. Reg. set Skip
Masked by MR1
Masked by MR2
Mem. at Addr.Reg. set Random
Masked by MR1
Masked by MR2
Memory at Address set Valid
Masked by MR1
Masked by MR2
Memory at Address set Empty
Masked by MR1
Masked by MR2
Memory at Address set Skip
Masked by MR1
Masked by MR2
Memory at Address set Random
Masked by MR1
Masked by MR2
Mem. at Highest-Prio. Match, Valid
Masked by MR1
Masked by MR2
Mem. at Highest-Prio. Match, Emp.
Masked by MR1
Masked by MR2
Mnemonic
SPD CR
SPD CR[MR1]
SPD CR[MR2]
SPD MR
SPD MR2
SPD M@[AR],V
SPD M@[AR][MR1],V
SPD M@[AR][MR2],V
SPD M@[AR],E
SPD M@[AR][MR1],E
SPD M@[AR][MR2],E
SPD M@[AR],S
SPD M@[AR][MR1],S
SPD M@[AR][MR2],S
SPD M@[AR],R
SPD M@[AR][MR1],R
SPD M@[AR][MR2],R
SPD M@aaaH,V
SPD M@aaaH[MR1],V
SPD M@aaaH[MR2],V
SPD M@aaaH,E
SPD M@aaaH[MR1],E
SPD M@aaaH[MR2],E
SPD M@aaaH,S
SPD M@aaaH[MR1],S
SPD M@aaaH[MR2],S
SPD M@aaaH,R
SPD M@aaaH[MR1],R
SPD M@aaaH[MR2],R
SPD M@HM,V
SPD M@HM[MR1],V
SPD M@HM[MR2],V
SPD M@HM,E
SPD M@HM[MR1],E
SPD M@HM[MR2],E
Op-Code
0100H
0140H
0180H
0108H
0110H
0124H
0164H
01A4H
0125H
0165H
01A5H
0126H
0166H
01A6H
0127H
0167H
01A7H
0924H
0964H
09A4H
0925H
0965H
09A5H
0926H
0966H
09A6H
0927H
0967H
09A7H
012CH
016CH
01ACH
012DH
016DH
01ADH
Instruction: Select Persistent Destination (continued)
Operation
Mem. at Highest-Prio. Match, Skip
Masked by MR1
Masked by MR2
Mem. at High.-Prio. Match, Random
Masked by MR1
Masked by MR2
Mem. at Next Free Addr., Valid
Masked by MR1
Masked by MR2
Mem. at Next Free Addr., Empty
MaskedbyMR1
MaskedbyMR2
Mem. at Next Free Addr., Skip
Masked by MR1
Masked by MR2
Mem. at Next Free Addr., Random
Masked by MR1
Masked by MR2
Mnemonic
SPD M@HM,S
SPD M@HM[MR1],S
SPD M@HM[MR2],S
SPD M@HM,R
SPD M@HM[MR1],R
SPD M@HM[MR2],R
SPD M@NF,V
SPD M@NF[MR1],V
SPD M@NF[MR2],V
SPD M@NF,E
SPD M@NF[MR1],E
SPD M@NF[MR2],E
SPD M@NF,S
SPD M@NF[MR1],S
SPD M@NF[MR2],S
SPD M@NF,R
SPD M@NF[MR1],R
SPD M@NF[MR2],R
Op-Code
012EH
016EH
01AEH
012FH
016FH
01AFH
0134H
0174H
01B4H
0135H
0175H
01B5H
0136H
0176H
01B6H
0137H
0177H
01B7H
Instruction: Temporary Command Override
Operation
Control Register
Page Address Register
Segment Control Register
Read Next Free Address
Address Register
Device Select Register
Read Persistent Source
Read Persistent Destination
Mnemonic
TCO CT
TCO PA
TCO SC
TCO NF
TCO AR
TCO DS
TCO PS
TCO PD
Op-Code
0200H
0208H
0210H
0218H
0220H
0228H
0230H
0238H
Instruction: Data Move
Operation
Comparand Register from:
No Operation
Mask Register 1
Mask Register 2
Memory at Address Reg.
Masked by MR1
Masked by MR2
Memory at Address
Masked by MR1
Masked by MR2
Mem. at Highest-Prio. Match
MaskedbyMR1
MaskedbyMR2
Mask Register 1 from:
Comparand Register
No Operation
Mask Register 2
Memory at Address Reg.
Memory at Address
Mem. at Highest-Prio. Match
Mnemonic
NOP
MOV CR,MR1
MOV CR,MR2
MOV CR,[AR]
MOV CR,[AR][MR1]
MOV CR,[AR][MR2]
MOV CR,aaaH
MOV CR,aaaH[MR1]
MOV CR,aaaH[MR2]
MOV CR,HM
MOV CR,HM[MR1]
MOV CR,HM[MR2]
MOV MR1,CR
NOP
MOV MR1,MR2
MOV MR1,[AR]
MOV MR1,aaaH
MOV MR1,HM
Op-Code
0300H
0301H
0302H
0304H
0344H
0384H
0B04H
0B44H
0B84H
0305H
0345H
0385H
0308H
0309H
030AH
030CH
0B0CH
030DH
20
Rev. 1
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