MT28F1284W18 Ver la hoja de datos (PDF) - Micron Technology
Número de pieza
componentes Descripción
Fabricante
MT28F1284W18 Datasheet PDF : 66 Pages
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8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Figure 27: WAIT# Signal in Burst Non-READ ARRAY Operation
CLK VIH
VIL
A0–A22 VIH
VIL
ADV# VIH
VIL
CE# VIH
VIL
OE# VIH
VIL
WE# VIH
VIL
WAIT# VOH
VOL
DQ0–DQ15 VOH
VO L
tAKS tAKH
Note 1
VALID
ADDRESS
tAVS
tVPH tVKS
tAVH
tVP
tCVS
tCKS
High-Z
tCEZ
tOEZ
Note 2
High-Z
tAOE
tACLK
tOD
tOD
VALID
OUTPUT
tOH
tKOH
High-Z
High-Z
UNDEFINED
NOTE:
1. Figure 6 on page 19 describes how to insert clock cycles during initial access.
2. WAIT# is shown active LOW, and WAIT# configured during delay (RCR8 = 0, RCR10 = 0).
READ Timing Parameters
SYMBOL
tAOE
tCEZ
tOEZ
tOD
tOH
tAVS
tCVS
tVP
tVPH
tAVH
-606
MIN
0
0
0
7
7
7
7
7
MAX
20
5
-705
MIN
0
0
0
7
7
7
7
7
MAX
30
20
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
tAKS
tVKS
tCKS
tACLK1
tACLK2
tKOH
tAKH
-606
MIN
7
7
7
3
7
MAX
11
20
NOTE:
1. Latency codes 3, 4, and 5.
2. Latency code 2.
-705
MIN
7
7
7
3
7
MAX
14
20
UNITS
ns
ns
ns
ns
ns
ns
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
51
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
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