CLK VIH
VIL
A0-A21 VIH
VIL
ADV#
VIH
VIL
VOH
DQ0-DQ15
VO L
VOH
DQ0-DQ15
VO L
VOH
DQ0-DQ15
VO L
VOH
DQ0-DQ15
VO L
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Figure 6: Latency Counter
VALID
ADDRESS
Code 2
Code 3
Code 4
Code 5
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
UNDEFINED
NOTE:
CLK shown as rising edge configuration (RCR6 = 1).
Table 10: Clock Frequency vs. First Access Latency
LATENCY COUNTER CODE
Frequency (MHz)
2
3
4/5
£40
£54
£66
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
19
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©2003 Micron Technology. Inc.