MT28F1284W18BQ-605BET Ver la hoja de datos (PDF) - Micron Technology
Número de pieza
componentes Descripción
Fabricante
MT28F1284W18BQ-605BET Datasheet PDF : 66 Pages
| |||
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
WAIT# Signal Function
When performing a continuous burst, or when per-
forming a four-, eight-, or 16-word burst with no wrap
selected (RCR3 = 1), the device may have an output
delay when the burst sequence crosses the first 16-
word boundary. The delay will occur only once during
any burst access. The starting address dictates the
amount of delay. If the starting address is at the end of
a 16-word boundary, the output delay will be the maxi-
mum delay. If the starting address is aligned with a 16-
word boundary, a delay will not be seen. Likewise, if a
burst never crosses a 16-word boundary, no delay will
be seen. For example, in a four-word burst, no-wrap
mode, possible linear burst sequences that do not
cause delays are:
0-1-2-3
1-2-3-4
2-3-4-5
3-4-5-6
4-5-6-7
5-6-7-8
6-7-8-9
7-8-9-10
8-9-10-11
9-10-11-12
10-11-12-13
11-12-13-14
12-13-14-15
The WAIT# signal informs the system if an output
delay occurs. When the WAIT# signal is asserted, it
indicates invalid data. When the WAIT# signal is deas-
serted, it indicates valid data. See Figure 26 for more
details.
The WAIT# output is high impedance until the
device is active (CE# = VIL). In asynchronous/page
mode, WAIT# is set to an asserted state (as defined by
RCR10). WAIT# is also set to an asserted state during
non-read-array BURST operations such as burst read
of status register, query, or device identifier.
During clock suspend, WAIT# remains active
because CE# gates the WAIT# signal. The WAIT# signal
does not revert to a high-impedance state when OE# is
de-asserted and therefore can cause contention with
another device attempting to control the system's
ready signal during a clock suspend. Multiple devices
should not be connected directly to the sysem's
READY ready signal if the clock suspend feature is
used.
Read Mode
The device supports two read configurations: burst
mode, and asynchronous/page mode. The RCR15 bit
(refer to Table 9) in the read configuration register sets
the read mode. Asynchronous/page mode is the
default read mode.
Latency Counter
The latency counter (RCR13–RCR11) provides the
number of clocks that must elapse after the clock edge
that starts the burst before data is valid, as shown in
Figure 6. This value depends on the input clock fre-
quency. See Table 10 for the clock frequency vs. first
access latency information.
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
Share Link: 