MT28F1284W18FQ-705BET Ver la hoja de datos (PDF) - Micron Technology
Número de pieza
componentes Descripción
Fabricante
MT28F1284W18FQ-705BET Datasheet PDF : 66 Pages
| |||
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Read Modes
The MT28F1284W18 supports two read configura-
tions: asynchronous/page mode and burst mode. The
RCR15 bit (see Table 9) in the read configuration regis-
ter sets the read configuration. At reset, asynchronous/
page mode is the default configuration for all READ
operations.
Asynchronous/Page Read Mode
Asynchronous/page read mode is the default read
configuration state. To use the device in an asynchro-
nous-only application, ADV# and CLK may be tied to
VSS, and WAIT# should be floated. Note that ADV# may
also be used in asynchronous mode to latch addresses
(latched asynchronous read mode).
A random access is initiated either on the falling
edge of CE#, on the falling edge of ADV#, or on a transi-
tion of the address lines (A0–A22), whichever occurs
last. Access times are given by tACE, tAADV, and tAA,
respectively.
A latched asynchronous read mode is also available
in which all address lines except A0–A3 are latched. In
this mode, the rising edge of ADV# will latch the
addresses. After the addresses are latched, this mode
becomes identical to the normal mode. The latched
mode is useful when noise is present on the address
lines, which might cause a READ operation from
unwanted locations.
Page mode is a performance-enhancing extension
to the legacy asynchronous READ operation. The ini-
tial portion of the page mode cycle is the same as the
asynchronous access cycle. Subsequent READs are
performed by holding CE# LOW and toggling A0–A3,
allowing random access of other words in the page.
These subsequent READs are done at the faster page
access time, tAPA.
Burst Read Mode
The burst read mode is used to achieve a faster data
rate than is possible with asynchronous read mode. A
burst access is started when an active clock edge
(defined by RCR6; refer to Table 9 for more informa-
tion) occurs after ADV# goes LOW. The address is
latched when ADV# goes HIGH or on the active clock
edge, whichever occurs first. The burst read configura-
tion is set in the read configuration register.
BURST READ operations can traverse partition
boundaries, but application code is responsible for
ensuring that the operations do not extend into parti-
tions that are programming or erasing. All blocks in all
partitions are burstable. For example, if a burst starts
in partition 0, the application can keep clocking until
the partition boundary is reached, and then read from
partition 1. If the application keeps clocking beyond
partition 15 last location, then the internal counter
restarts from partition 0 first address (see Figure 5).
Figure 5: Partition Boundary Wrapping
(Bottom Boot Example)
Partition 0 start address
00000h
Partition 0 end address
Partition 1 start address
07FFFFh
080000h
Partition 1 end address
...
Partition 15 start address
0FFFFFh
780000h
Partition 0
Partition boundary
Partition 15
Partition 15 end address
7FFFFFh
Clock Suspend
The clock suspend feature enables the device to sus-
pend a burst sequence, to allow data to be retrieved
from another device sharing the same bus. The system
processor can resume the burst sequence where it left
off at a later time, with zero initial access latency pen-
alty. Clock suspend is most beneficial in non-cached
systems.
Clock suspend can occur at any stage of a burst,
during initial access latency, or when outputting data.
When a burst access is suspended, internal array sens-
ing continues, and any previously latched internal
data is retained. As long as the device operation condi-
tions are met, a burst sequence can be suspended and
resumed without any limit.
Clock suspend is executed when CE# is asserted, the
current address has been latched (either ADV# rising
edge or CLK edge), CLK is halted, and OE# is de-
asserted. CLK can be halted when it is at VIH or VIL. To
resume, OE# is re-asserted and CLK is restarted. Sub-
sequent CLK edges resume the burst sequence where
it left off.
Note that when using the clock suspend feature, the
device’s WAIT# signal remains active. Multiple devices
should not share the systems’s READY signal when
using the clock suspend feature. Refer to the WAIT#
signal configuration on RCR8.
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
Share Link: 