MT28F1284W18FQ-605BET Ver la hoja de datos (PDF) - Micron Technology
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MT28F1284W18FQ-605BET Datasheet PDF : 66 Pages
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8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Table 6: Command Codes and Descriptions
OPERATION
READ
PROGRAM
ERASE
SUSPEND
CODE
FFh
70h
90h
98h
50h
40h
10h
30h
D0h
20h
D0h
B0h
D0h
DEVICE
MODE
Read Array
Read Status
Register
Read Device
Identifier
Read Query
Clear Status
Register
Program
Setup
Program
Setup
FPA Setup
FPA Confirm
Erase Setup
Erase Confirm
Program/Erase
Suspend
Program/Erase
Resume
BUS
CYCLE
DESCRIPTION
First Places the addressed partition in read array mode.
First This command places the addressed partition into read status
register mode. Reading the partition will output the contents of the
status register for the addressed partition. The device will
automatically enter this mode for the addressed partition after a
PROGRAM or ERASE operation has been initiated.
First Puts the addressed partition into the read device identifier mode so
that reading the device will output the manufacturer/device codes,
configuration register data, block lock status, or protection register
data on DQ0–DQ15.
First Puts the addressed partition into the read query mode so that
reading the partition will output common flash interface
information.
First The WSM can set the block lock status (SR1), VPP status (SR3),
program status (SR4), and erase status (SR5) bits in the status register
to “1,” but it cannot clear them to “0.” SR1, SR3, SR4, and SR5 can
only be cleared by a device reset or by using the CLEAR STATUS
REGISTER command.
First A two-cycle command: The first cycle prepares for a PROGRAM
operation, and the second cycle latches addresses and data and
initiates the WSM to execute the program algorithm. After the
second cycle, the device outputs status register data on the falling
edge of OE# or CE#, whichever occurs last.
First Equivalent to Program Setup (40h).
First
Second
First
Second
First
First
This program command activates FPA mode. The first cycle prepares
for FPA operation. If the second cycle is an FPA CONFIRM
COMMAND (D0h), subsequent WRITEs provide program data. All
other commands are ignored once FPA mode begins.
If the previous command was FPA SETUP (30h), the CSM latches the
address and data and prepares the device for FPA mode.
Prepares the CSM for the ERASE CONFIRM command. If the next
command is not ERASE CONFIRM, the CSM will set both SR4 and SR5
of the status register to a “1,” place the partition into read status
register mode, and wait for another command.
If the previous command was an ERASE SETUP command, then the
CSM will close the address and data latches, and it will begin erasing
the block indicated on the address pins. The device will then output
status register data on the falling edge of OE# or CE#, whichever
occurs last.
Issuing this command will suspend the currently executing
PROGRAM/ERASE operation. The status register will indicate when
the operation has been successfully suspended by setting either the
program suspend (SR2) or erase suspend (SR6), and the WSM status
bit (SR7) to a “1” (ready). The WSM will continue to idle in the
suspend state, regardless of the state of all input control signals
except RST#, which will immediately reset the WSM and the
remainder of the chip if RST# is driven to VIL.
If a PROGRAM or ERASE operation is suspended (as indicated by SR2
or SR6), this command will resume the operation.
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
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