MPC9600 Ver la hoja de datos (PDF) - Motorola => Freescale
Número de pieza
componentes Descripción
Fabricante
MPC9600 Datasheet PDF : 16 Pages
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Freescale Semiconductor, Inc.
Table 4: DC CHARACTERISTICS (VCC = 2.5 V ±5%, TA = –40° to +85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VIH
Input High Voltage
1.7
VCC + 0.3
V
LVCMOS
VIL
Input Low Voltage
0.7
V
LVCMOS
VPP
Peak-to-peak input voltage (DC) PCLK, PCLK
250
VCMRa
Common Mode Range (DC)
PCLK, PCLK
1.0
VOH
Output High Voltage
1.8
mV
LVPECL
VCC-0.6
V
LVPECL
V
IOH=-15 mAb
VOL
ZOUT
Output Low Voltage
Output Impedance
0.6
17 – 20
V
IOL= 15 mA
W
IIN
Input Leakage Current
±150
µA
VIN = VCC or GND
ICCA
Maximum PLL Supply Current
3.0
5.0
mA
VCCA Pin
ICCQ
Maximum Quiescent Supply Current
1.0
mA
All VCC Pins
a. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (DC) specification.
b. The MPC9600 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 Ω series terminated transmission lines per
output.
Table 5: AC CHARACTERISTICS (VCC = 3.3 V ±5% or VCC = 2.5 V ±5%, TA = –40° to +85°C)a
Symbol
Characteristics
Min
Typ
Max
Unit
fref
Input Frequency
B8 feedback (FSEL_FB=0)
B12 feedback (FSEL_FB=1)
25
16.67
50
MHz
33
MHz
Condition
PLL locked
PLL locked
Static test mode (VCCA = GND)
0
fVCO
fMAX
VCO Frequency
200
BB Maximum Output Frequency
2 outputs (FSELx=0)
4 outputs (FSELx=1)
100
50
frefDC
Reference Input Duty Cycle
25
VPP
Peak-to-peak Input Voltage
PCLK, PCLK
500
VCMRb
Common Mode Range
PCLK, PCLK (VCC = 3.3 V ±5%)
1.2
PCLK, PCLK (VCC = 2.5 V ±5%)
1.2
tr, tf
CCLK Input Rise/Fall Time
t(∅)
Propagation Delay (static phase offset)
CCLK to FB_IN
–60
PECL_CLK to FB_IN
+30
tsk(o)
Output-to-output Skew
all outputs, single frequency
all outputs, multiple frequency
within QAx output bank
within QBx outputs
within QCx outputs
DC
Output Duty Cycle
45
tr, tf
Output Rise/Fall Time
0.1
tPLZ, HZ Output Disable Time
tPZL, ZH Output Enable Time
BW
PLL Closed Loop Bandwidth
B8 feedback (FSEL_FB=0)
B12 feedback (FSEL_FB=1)
500
MHz VCCA = GND
400
MHz
200
100
75
1000
MHz
MHz
%
mV
PLL locked
PLL locked
LVPECL
VCC-0.8
V
LVPECL
VCC-0.6
V
LVPECL
1.0
ns
see Figure 12
+40
+130
+140
+230
ps
PLL locked
ps
PLL locked
70
150
ps
Measured at
70
150
ps
coincident
rising edge
30
75
ps
40
125
ps
30
75
ps
50
55
%
1.0
ns
see Figure 12
10
ns
10
ns
1.0 – 10
0.6 – 4.0
MHz
MHz
–3 dB point of
PLL transfer
characteristic
TIMING SOLUTIONS
For More Informa5tion On This Product,
Go to: www.freescale.com
MOTOROLA
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