MC68HCP11A1MP2(1996) Ver la hoja de datos (PDF) - Motorola => Freescale

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MC68HCP11A1MP2
(Rev.:1996)

HCMOS Single-Chip Microcontroller

Motorola => Freescale 

2.1.4 E Clock Output (E)

This is the output connection for the internally generated E clock which can be used

as a timing reference. The frequency of the E clock output is actually one fourth that

of the input frequency at the XTAL and EXTAL pins. When the E clock output is low

an internal process is taking place and, when high, data is being accessed. The E

clock signal is halted when the MCU is in STOP mode.

2.1.5 Interrupt Request (IRQ)

The IRQ input provides a means for requesting asynchronous interrupts to the

MC68HC11A8. It is program selectable (OPTION register) with a choice of either neg-

ative edge-sensitive or level-sensitive triggering, and is always configured to level-

sensitive triggering by reset. The IRQ pin requires an external pull-up resistor to VDD

(typically 4.7K ohm).

2.1.6 Non-Maskable Interrupt (XIRQ)

This input provides a means for requesting a non-maskable interrupt, after reset ini-

tialization. During reset, the X bit in the condition code register is set and any interrupt

is masked until MCU software enables it. The XIRQ input is level sensitive and re-

quires an external pull-up resistor to VDD.

2.1.7 Mode A/Load Instruction Register and Mode B/Standby Voltage (MODA/LIR,

MODB/VSTBY)

During reset, MODA and MODB are used to select one of the four operating modes.

Refer to Table 2-1. Paragraph 2.2 Operating Modes provides additional information.

2

Table 2-1 Operating Modes vs. MODA and MODB

MODB

1

1

0

0

MODA

0

1

0

1

Mode Selected

Single Chip

Expanded Multiplexed

Special Bootstrap

Special Test

After the operating mode has been selected, the LIR pin provides an open-drain output

to indicate that an instruction is starting. All instructions are made up of a series of E

clock cycles. The LIR signal goes low during the first E clock cycle of each instruction

(opcode fetch). This output is provided as an aid in program debugging.

The VSTBY signal is used as the input for RAM standby power. When the voltage on

this pin is more than one MOS threshold (about 0.7 volts) above the VDD voltage, the

internal 256-byte RAM and part of the reset logic are powered from this signal rather

than the VDD input. This allows RAM contents to be retained without VDD power applied

to the MCU. Reset must be driven low before VDD is removed and must remain low

until VDD has been restored to a valid level.

MC68HC11A8

TECHNICAL DATA

SIGNAL DESCRIPTIONS AND OPERATING MODES

MOTOROLA

2-3

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