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MAX9238EUM

Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers

Maxim Integrated 

MAX9234/MAX9236/MAX9238

Hot-Swappable, 21-Bit, DC-Balanced LVDS

Deserializers

In the following example, the capacitor value for a

droop of 2% is calculated. Jitter due to this droop is

then calculated assuming a 1ns transition time:

C = - (2 x tB x DSV) / (ln (1 - D) x (RT + RO)) (Eq 1)

where:

C = AC-coupling capacitor (F).

tB = bit time (s).

DSV = digital sum variation (integer).

ln = natural log.

D = droop (% of signal amplitude).

RT = termination resistor (Ω).

RO = output resistance (Ω).

Equation 1 is for two series capacitors (Figure 10). The

bit time (tB) is the period of the parallel clock divided by

9. The DSV is 10. See equation 3 for four series capaci-

tors (Figure 11).

The capacitor for 2% maximum droop at 8MHz parallel

rate clock is:

C = - (2 x tB x DSV) / (ln (1 - D) x (RT + RO))

C = - (2 x 13.9ns x 10) / (ln (1 - 0.02) x (100Ω + 78Ω))

C = 0.0773µF

Jitter due to droop is proportional to the droop and

transition time:

tJ = tT x D (Eq 2)

where:

tJ = jitter (s).

tT = transition time (s) (0 to 100%).

D = droop (% of signal amplitude).

Jitter due to 2% droop and assumed 1ns transition time is:

tJ = 1ns x 0.02

tJ = 20ps

The transition time in a real system depends on the fre-

quency response of the cable driven by the serializer.

The capacitor value decreases for a higher frequency

parallel clock and for higher levels of droop and jitter.

Use high-frequency, surface-mount ceramic capacitors.

Equation 1 altered for four series capacitors (Figure 11) is:

C = - (4 x tB x DSV) / (ln (1 - D) x (RT + RO)) (Eq 3)

Input Bias and Frequency Detection

The inverting and noninverting LVDS inputs are internally

connected to +1.2V through 42kΩ (min) to provide bias-

ing for AC-coupling (Figure 1). A frequency-detection

circuit on the clock input detects when the input is not

switching, or is switching at low frequency. In this case,

all outputs are driven low. To prevent switching due to

noise when the clock input is not driven, bias the clock

input to differential +15mV by connecting a 10kΩ ±1%

Maxim Integrated

pullup resistor between the noninverting input and VCC,

and a 10kΩ ±1% pulldown resistor between the invert-

ing input and ground. These bias resistors, along with

the 100Ω ±1% tolerance termination resistor, provide

+15mV of differential input.

Unused LVDS Data Inputs

At each unused LVDS data input, pull the inverting input

up to VCC using a 10kΩ resistor, and pull the noninverting

input down to ground using a 10kΩ resistor. Do not con-

nect a termination resistor. The pullup and pulldown resis-

tors drive the corresponding outputs low and prevent

switching due to noise.

PWRDWN

Driving PWRDWN low puts the outputs in high imped-

ance, stops the PLL, and reduces supply current to

50µA or less. Driving PWRDWN high drives the outputs

low until the PLL locks. The outputs of two deserializers

can be bused to form a 2:1 mux with the outputs con-

trolled by PWRDWN. Wait 100ns between disabling one

deserializer (driving PWRDWN low) and enabling the

second one (driving PWRDWN high) to avoid con-

tention of the bused outputs.

Input Clock and PLL Lock Time

There is no required timing sequence for the applica-

tion or reapplication of the parallel rate clock (RxCLK

IN) relative to PWRDWN, or to a power-supply ramp for

proper PLL lock. The PLL lock time is set by an internal

counter. The maximum time to lock is 32,800 clock

periods. Power and clock should be stable to meet the

lock-time specification. When the PLL is locking, the

outputs are low.

Power-Supply Bypassing

There are separate on-chip power domains for digital

circuits, outputs, PLL, and LVDS inputs. Bypass each

VCC, VCCO, PLL VCC, and LVDS VCC pin with high-fre-

quency, surface-mount ceramic 0.1µF and 0.001µF

capacitors in parallel as close to the device as possi-

ble, with the smallest value capacitor closest to the

supply pin.

Cables and Connectors

Interconnect for LVDS typically has a differential imped-

ance of 100Ω. Use cables and connectors that have

matched differential impedance to minimize impedance

discontinuities.

Twisted-pair and shielded twisted-pair cables offer

superior signal quality compared to ribbon cable and

tend to generate less EMI due to magnetic field cancel-

ing effects. Balanced cables pick up noise as common

mode, which is rejected by the LVDS receiver.

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