MAX7314ATG Ver la hoja de datos (PDF) - Maxim Integrated

Número de pieza

componentes Descripción

Fabricante

MAX7314ATG

18-Port GPIO with LED Intensity Control, Interrupt, and Hot-Insertion Protection

Maxim Integrated 

18-Port GPIO with LED Intensity Control,

Interrupt, and Hot-Insertion Protection

Table 4. Configuration Register (continued)

REGISTER

ADDRESS

CODE

REGISTER DATA

(hex)

D7

D6

D5

D4

D3

D2

D1

D0

R/W

CONFIGURATION

Write device configuration

0

Read back device configuration

1

INT BLINK O1

O0

I

G

B

E

Read back BLINK input pin status—

input is low

1

X

0

X

X

X

X

X

X

0x0F

Read back BLINK input pin status—

input is high

1

X

1

X

X

X

X

X

X

Read back data change interrupt status

—data change is not detected, and

INT/O16 output is high when interrupt

1

enable (I bit) is set

0

X

X

X

X

X

X

X

Read back data change interrupt status

—data change is detected, and INT/O16

1

output is low when interrupt enable (I bit) is set

X = Don’t care.

1

X

X

X

X

X

X

X

Blink Mode

In blink mode, the output ports can be flipped between

using either the blink phase 0 registers or the blink

phase 1 registers. Flip control is both hardware (the

BLINK input) and software control (the blink flip flag B

in the configuration register) (Table 4).

The blink function can be used for LED effects by pro-

gramming different display patterns in the two sets of

output port registers, and using the software or hard-

ware controls to flip between the patterns.

If the blink phase 1 registers are written with 0xFF, then

the BLINK input can be used as a hardware disable to,

for example, instantly turn off an LED pattern pro-

grammed into the blink phase 0 registers. This tech-

nique can be further extended by driving the BLINK

input with a PWM signal to modulate the LED current to

provide fading effects.

The blink mode is enabled by setting the blink enable flag

E in the configuration register (Table 4). When blink mode

is enabled, the states of the blink flip flag and the BLINK

input are EXOR’ed to set the phase, and the output ports

are set by either the blink phase 0 registers or the blink

phase 1 registers (Figure 11) (Table 7).

The blink mode is disabled by clearing the blink enable

flag E in the configuration register (Table 4). When blink

mode is disabled, the state of the blink flip flag is

ignored, and the blink phase 0 registers alone control

the output ports.

Blink Phase Registers

When the blink function is disabled, the two blink phase

0 registers set the logic levels of the 16 ports (P0

through P15) when configured as outputs (Table 8). A

duplicate pair of registers called the blink phase 1 reg-

isters are also used if the blink function is enabled (Table

9). A logic high sets the appropriate output port high

impedance, while a logic low makes the port go low.

BLINK ENABLE FLAG E

BLINK FLIP FLAG B

BLINK INPUT

Figure 11. Blink Logic

BLINK PHASE REGISTERS

14 ______________________________________________________________________________________

Share Link: