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MAX7031

Low-Cost, 308MHz, 315MHz, and 433.92MHz FSK Transceiver with Fractional-N PLL

Maxim Integrated 

Low-Cost, 308MHz, 315MHz, and 433.92MHz

FSK Transceiver with Fractional-N PLL

Table 1. AGC Dwell Time Settings for

MAX7031

AGC1

0

0

1

1

AGC0

0

1

0

1

DESCRIPTION

AGC disabled, high gain selected

K = 11, short dwell time

K = 14, medium dwell time

K = 20, long dwell time

The MAX7031 uses the two AGC control pins (AGC0

and AGC1) to enable or disable the AGC and set three

user-controlled dwell timer settings. The AGC dwell

time is dependent on the crystal frequency and the bit

settings of the AGC control pins. To calculate the dwell

time, use the following equation:

Dwell Time = 2K

fXTAL

where K is an integer in decimal, determined by the

control pin settings shown in Table 1.

For example, a receiver operating at 315MHz has a

crystal oscillator frequency of 12.679MHz. For K = 11

(AGC setting = 0, 1), the dwell timer is 162µs; for K =

14 (AGC setting = 1, 0), the dwell timer is 1.3ms; for K

= 20 (AGC setting = 1, 1), the dwell time is 83ms.

Mixer

A unique feature of the MAX7031 is the integrated

image rejection of the mixer. This eliminates the need

for a costly front-end SAW filter for many applications.

The advantage of not using a SAW filter is increased

sensitivity, simplified antenna matching, less board

space, and lower cost.

The mixer cell is a pair of double-balanced mixers that

perform an IQ downconversion of the RF input to the

10.7MHz intermediate frequency (IF) with low-side

injection (i.e., fLO = fRF - fIF). The image-rejection circuit

then combines these signals to achieve a typical 46dB

of image rejection over the full temperature range. Low-

side injection is required as high-side injection is not

possible due to the on-chip image rejection. The IF out-

put is driven by a source follower, biased to create a

driving impedance of 330Ω to interface with an off-chip

330Ω ceramic IF filter. The voltage conversion gain dri-

ving a 330Ω load is approximately 20dB. Note that the

MIXIN+ and MIXIN- inputs are functionally identical.

Integer-N, Phase-Locked Loop (PLL)

The MAX7031 utilizes a fixed integer-N PLL to generate

the receive LO. All PLL components, including the loop

filter, voltage-controlled oscillator, charge pump, asyn-

chronous 24x divider, and phase-frequency detector

are internal. The loop bandwidth is approximately

500kHz. The relationship between RF, IF, and reference

frequencies is given by:

fREF = (fRF - fIF)/24

Intermediate Frequency (IF)

The IF section presents a differential 330Ω load to pro-

vide matching for the off-chip ceramic filter. The internal

six AC-coupled limiting amplifiers produce an overall

gain of approximately 65dB, with a bandpass filter-type

response centered near the 10.7MHz IF frequency with

a 3dB bandwidth of approximately 10MHz. The RSSI

circuit demodulates the IF to baseband by producing a

DC output proportional to the log of the IF signal level

with a slope of approximately 15mV/dB.

FSK Demodulator

The FSK demodulator uses an integrated 10.7MHz PLL

that tracks the input RF modulation and converts the

frequency deviation into a voltage difference. The PLL

is illustrated in Figure 1. The input to the PLL comes

from the output of the IF limiting amplifiers. The PLL

control voltage responds to changes in the frequency

of the input signal with a nominal gain of 2.0mV/kHz.

For example, an FSK peak-to-peak deviation of 50kHz

IF

LIMITING

AMPS

PHASE

DETECTOR

CHARGE

PUMP

TO FSK BASEBAND FILTER

AND DATA SLICER

LOOP

FILTER

10.7MHz VCO

2.0mV/kHz

MAX7031

FSK

DEMOD

100kΩ

100kΩ

DS+

OP+

DF

CF2

CF1

Figure 1. FSK Demodulator PLL Block Diagram

Figure 2. Sallen-Key Lowpass Data Filter

12 ______________________________________________________________________________________

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