MAX5019 Ver la hoja de datos (PDF) - Maxim Integrated
Número de pieza
componentes Descripción
Fabricante
MAX5019 Datasheet PDF : 14 Pages
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Current-Mode PWM Controllers with Integrated
Startup Circuit
VDSMAX ≥ 72V × 1
+
14
14
= 144V
Choose MOSFETs with appropriate avalanche
power ratings.
5) Choose the tertiary winding turns ratio (NT/NP) so
that the minimum input voltage provides the mini-
mum operating voltage at VDD (13V). Use the follow-
ing equation to calculate the tertiary winding turns
ratio:
VDDMIN + 0.7
VIN_MIN
× NP
≤
NT
≤
VDDMAX + 0.7
VIN_MAX
× NP
where:
VDDMIN is the minimum VDD supply voltage (13V).
VDDMAX is the maximum VDD supply voltage (36V).
VIN_MIN is the minimum input supply voltage (36V).
VIN_MAX is the maximum input supply voltage (72V
in this design example).
NP is the number of turns of the primary winding.
NT is the number of turns of the tertiary winding.
13.7
36
× 14
≤
NT
≤
36.7
72
× 14
5.33 ≤ NT ≤ 7.14
Choose NT = 6.
6) Choose RSENSE according to the following equation:
RSENSE
≤
NS
NP
VILIM
×1.2 × IOUTMAX
where:
VILim is the current-sense comparator trip threshold
voltage (0.465V).
NS/NP is the secondary side turns ratio (5/14 in this
example).
IOUTMAX is the maximum DC output current (10A in
this example).
RSENSE ≤
5
0.465V
×1.2 ×10
=
109mΩ
14
7) Choose the inductor value so that the peak ripple
current (LIR) in the inductor is between 10% and
20% of the maximum output current.
L ≥ (VOUT + VD ) × (1-DMIN)
2 × LIR × 275kHz × IOUTMAX
where VD is the output Schottky diode forward volt-
age drop (0.5V).
L ≥ (5.5) × (1- 0.198) = 4.01µH
0.4 × 275kHz ×10A
8) The size and ESR of the output filter capacitor deter-
mine the output ripple. Choose a capacitor with a
low ESR to yield the required ripple voltage.
Use the following equations to calculate the peak-to-
peak output ripple:
VRIPPLE = VR2IPPLE,ESR + VR2IPPLE,C
where:
VRIPPLE is the combined RMS output ripple due to
VRIPPLE,ESR, the ESR ripple, and VRIPPLE,C, the
capacitive ripple. Calculate the ESR ripple and
capacitive ripple as follows:
VRIPPLE,ESR = IRIPPLE x ESR
VRIPPLE,C = IRIPPLE/(2 x π x 275kHz x COUT)
Layout Recommendations
All connections carrying pulsed currents must be very
short, be as wide as possible, and have a ground plane
as a return path. The inductance of these connections
must be kept to a minimum due to the high di/dt of the
currents in high-frequency switching power converters.
Current loops must be analyzed in any layout pro-
posed, and the internal area kept to a minimum to
reduce radiated EMI. Ground planes must be kept as
intact as possible.
Chip Information
TRANSISTOR COUNT: 589
PROCESS: BiCMOS
12 ______________________________________________________________________________________
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