MAX3542 Ver la hoja de datos (PDF) - Maxim Integrated

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MAX3542

Complete Single-Conversion Television Tuner

Maxim Integrated 

Complete Single-Conversion

Television Tuner

Write Cycle

When addressed with a write command, the MAX3542

allows the master to write to a single register or to multi-

ple successive registers.

A write cycle begins with the bus master issuing a

START condition followed by the seven slave address

bits and a write bit (R/W = 0). The MAX3542 issues an

ACK if the slave address byte is successfully received.

The bus master must then send to the slave the

address of the first register it wishes to write to. If the

slave acknowledges the address, the master can then

write one byte to the register at the specified address.

Data is written beginning with the most significant bit.

The MAX3542 again issues an ACK if the data is suc-

cessfully written to the register. The master can contin-

ue to write data to the successive internal registers with

the MAX3542 acknowledging each successful transfer,

or it can terminate transmission by issuing a STOP con-

dition. The write cycle does not terminate until the mas-

ter issues a STOP condition.

Figure 2 illustrates an example in which registers 0

through 2 are written with 0x0E, 0xD8, and 0xE1,

respectively.

Read Cycle

A read cycle begins with the bus master issuing a

START condition followed by the seven slave address

bits and a write bit (R/W = 0). The MAX3542 issues an

ACK if the slave address byte is successfully

received. The master then sends the 8-bit address of

the first register that it wishes to read. The MAX3542

then issues another ACK. Next, the master must issue

a START condition followed by the seven slave

address bits and a read bit (R/W = 1). The MAX3542

issues an ACK if it successfully recognizes its address

and begins sending data from the specified register

address starting with the most significant bit (MSB).

Data is clocked out of the MAX3542 on the rising edge

of SCL. On the 9th rising edge of SCL, the master can

issue an ACK and continue reading successive regis-

ters or it can issue a NACK followed by a STOP condi-

tion to terminate transmission. The read cycle does

not terminate until the master issues a STOP condi-

tion. Figure 3 illustrates an example in which registers

0 and 1 are read back.

START

WRITE DEVICE

ADDRESS

R/W

ACK

WRITE REGISTER

ADDRESS

ACK

WRITE DATA TO

REGISTER 0x00

ACK

WRITE DATA TO

REGISTER 0x01

ACK

WRITE DATA TO

REGISTER 0x02

ACK

STOP

11000[ADDR2][ADDR1] 0 —

0x00

—

0x0E

—

0xD8

—

0xE1

—

Figure 2. Example: Write Registers 0 through 2 with 0x0E, 0xD8, and 0xE1, Respectively

START

WRITE DEVICE

ADDRESS

R/W

ACK

WRITE 1ST REGISTER

ADDRESS

ACK

START

WRITE DEVICE

ADDRESS

R/W ACK

READ DATA

REG 0

ACK

READ DATA

REG 1

NACK

STOP

11000[ADDR2][ADDR1] 0 —

0x00

—

11000[ADDR2][ADDR1] 1 — D7–D0 — D7–D0 —

Figure 3. Example: Read Data from Registers 0 and 1

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