MAX1211(2003) Ver la hoja de datos (PDF) - Maxim Integrated

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MAX1211
(Rev.:2003)

65Msps, 12-Bit, IF Sampling ADC

Maxim Integrated 

65Msps, 12-Bit, IF Sampling ADC

ance state within 10ns of the rising edge of PD and

becomes active within 10ns of PD’s falling edge.

Digital Output Data (D0–D11), Output Format (G/T)

The MAX1211 provides a 12-bit, parallel, tri-state out-

put bus. D0–D11 and DOR update on the falling edge

of DAV and are valid on the rising edge of DAV.

The MAX1211 output data format is either Gray code or

two’s complement, depending on the logic input G/T.

With G/T high, the output data format is Gray code.

With G/T low, the output data format is two’s comple-

ment. See Figure 8 for a binary-to-Gray and Gray-to-

binary code-conversion example.

The following equations, Table 2, Figure 6, and Figure 8

define the relationship between the digital output and

the analog input:

VINP

−

VINN

=

(VREFP

−

VREFN)

×

2

×

CODE10 −

4096

2048

for Gray code (G/T = 1).

0x7FF

0x7FE

0x7FD

1 LSB = 2 x VREF

4096

VREF

VREF = VREFP - VREFN

VREF

0x001

0x000

0xFFF

0x803

0x802

0x801

0x800

-2047 -2045

-1 0 +1

+2045 +2047

DIFFERENTIAL INPUT VOLTAGE (LSB)

VINP

−

VINN

=

(VREFP

−

VREFN)

×

2

×

CODE10

4096

for two’s complement (G/T = 0).

where CODE10 is the decimal equivalent of the digital

output code as shown in Table 2.

The digital outputs D0–D11 are high impedance when

the MAX1211 is in power-down (PD = high). D0–D11

go high impedance within 10ns of the rising edge of PD

and become active within 10ns of PD’s falling edge.

Keep the capacitive load on the MAX1211 digital out-

puts D0–D11 as low as possible (<15pF) to avoid large

digital currents feeding back into the analog portion of

the MAX1211 and degrading its dynamic performance.

The addition of external digital buffers on the digital

outputs isolate the MAX1211 from heavy capacitive

loads. To improve the dynamic performance of the

MAX1211, add 220Ω resistors in series with the digital

outputs close to the MAX1211. Refer to the MAX1211

EV kit schematic for an example of the digital outputs

driving a digital buffer through 220Ω series resistors.

Power-Down Input (PD)

The MAX1211 has two power modes that are controlled

with power-down digital input (PD). With PD low, the

MAX1211 is in its normal operating mode. With PD

high, the MAX1211 is in power-down mode.

The power-down mode allows the MAX1211 to efficient-

ly use power by transitioning to a low-power state when

conversions are not required. Additionally, the

MAX1211 parallel output bus goes high impedance in

Figure 6. Two’s Complement Transfer Function (G/T = 0)

0x800

0x801

0x803

1 LSB = 2 x VREF

4096

VREF

VREF = VREFP - VREFN

VREF

0xC01

0xC00

0x400

0x002

0x003

0x001

0x000

-2047 -2045

-1 0 +1

+2045 +2047

DIFFERENTIAL INPUT VOLTAGE (LSB)

Figure 7. Gray Code Transfer Function (G/T = 1)

power-down mode, allowing other devices on the bus

to be accessed.

In power-down mode, all internal circuits are off, the

analog supply current reduces to 4mA, and the digital

supply current reduces to 19µA. The following list

______________________________________________________________________________________ 21

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