M50FLW080A Ver la hoja de datos (PDF) - STMicroelectronics

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M50FLW080A

8-Mbit (13 x 64-Kbyte Blocks + 3 × 16 × 4 Kbyte Sectors) 3-V supply, Firmware Hub / low-pin-count Flash memory

STMicroelectronics 

Summary description

M50FLW080A, M50FLW080B

Figure 1. Logic diagram (FWH/LPC interface)

VCC VPP

4

ID0-ID3

5

GPI0-

GPI4

4

FWH0/LAD0

FWH3/LAD3

WP

FWH4/LFRAME M50FLW080A

TBL

M50FLW080B

CLK

IC

RP

INIT

VSS

AI09229B

Table 1. Signal names (FWH/LPC interface)

FWH0/LAD0-FWH3/LAD3

Input/Output Communications

FWH4/LFRAME

Input Communication Frame

ID0-ID3

Identification Inputs

(ID0 and ID1 are Reserved for Future Use (RFU) in LPC mode)

GPI0-GPI4

General Purpose Inputs

IC

Interface Configuration

RP

Interface Reset

INIT

CPU Reset

CLK

Clock

TBL

Top Block Lock

WP

Write Protect

RFU

Reserved for Future Use. Leave disconnected

VCC

Supply Voltage

VPP

Optional Supply Voltage for Fast Program and Erase Operations

VSS

Ground

NC

Not Connected Internally

8/64

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