M41T00AUDD1F Ver la hoja de datos (PDF) - STMicroelectronics

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M41T00AUDD1F

Serial real-time clock (RTC) with audio

STMicroelectronics 

M41T00AUD

Operation

4.4

WRITE mode

In this mode the master transmitter transmits to the M41T00AUD slave receiver. Bus

protocol is shown in Figure 11. Following the START condition and slave address, a logic '0'

(R/W = 0) is placed on the bus and indicates to the addressed device that word address An

will follow and is to be written to the on-chip address pointer. The data word to be written to

the device is strobed in next and the internal address pointer is incremented to the next

location within the device on the reception of an acknowledge clock. The M41T00AUD slave

receiver will send an acknowledge clock to the master transmitter after it has received the

slave address and again after it has received the word address and each data byte (see

Figure 8).

Figure 11. WRITE mode sequence

BUS ACTIVITY:

MASTER

SDA LINE

S

WORD

ADDRESS (An)

BUS ACTIVITY:

SLAVE

ADDRESS

DATA n

DATA n+1

DATA n+X P

AI00591

4.5

Data retention mode

With valid VCC applied, the M41T00AUD can be accessed as described above with READ

or WRITE cycles. Should the supply voltage decay, the M41T00AUD will automatically

deselect, write protecting itself when VCC falls (see Figure 13).

Doc ID 13480 Rev 5

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