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28F008C3 Datasheet PDF : 59 Pages
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E
3 VOLT ADVANCED+ BOOT BLOCK
Table 9. Block Locking State Transitions
Current State
Erase/Prog Lock Command Input Result [Next State]
WP# DQ1 DQ0
Name
Allowed?
Lock
Unlock
Lock-Down
0
0
0
“Unlocked”
Yes
Goes To [001] No Change Goes To [011]
0
0
1
“Locked” (Default)
No
No Change Goes To [000] Goes To [011]
0
1
1
“Locked-Down”
No
No Change No Change No Change
1
0
0
“Unlocked”
Yes
Goes To [101] No Change Goes To [111]
1
0
1
“Locked”
No
No Change Goes To [100] Goes To [111]
1
1
0 Lock-Down Disabled
Yes
Goes To [111] No Change Goes To [111]
1
1
1 Lock-Down Disabled
No
No Change Goes To [110] No Change
NOTES:
1. In this table, the notation [XYZ] denotes the locking state of a block, where X = WP#, Y = DQ1, and Z = DQ0. The current
locking state of a block is defined by the state of WP# and the two bits of the block lock status (DQ0, DQ1). DQ0 indicates if
a block is locked (1) or unlocked (0). DQ1 indicates if a block has been locked-down (1) or not (0).
2. At power-up or device reset, all blocks default to Locked state [001] (if WP# = 0). Holding WP# = 0 is the recommended
default.
3. The “Erase/Program Allowed?” column shows whether erase and program operations are enabled (Yes) or disabled (No)
in that block’s current locking state.
4. The “Lock Command Input Result [Next State]” column shows the result of writing the three locking commands (Lock,
Unlock, Lock-Down) in the current locking state. For example, “Goes To [001]” would mean that writing the command to a
block in the current locking state would change it to [001].
3.4 128-Bit Protection Register
The Advanced+ Boot Block architecture includes a
128-bit protection register than can be used to
increase the security of a system design. For
example, the number contained in the protection
register can be used to “mate” the flash component
with other system components such as the CPU or
ASIC, preventing device substitution. Additional
application information can be found in Intel
application note AP-657 Designing with the
Advanced+ Boot Block Flash Memory Architecture.
The 128-bits of the protection register are divided
into two 64-bit segments. One of the segments is
programmed at the Intel factory with a unique 64-bit
number, which is unchangeable. The other segment
is left blank for customer designs to program as
desired. Once the customer segment is
programmed, it can be locked to prevent
reprogramming.
3.4.1
READING THE PROTECTION
REGISTER
The protection register is read in the configuration
read mode. The device is switched to this mode by
writing the Read Configuration command (90H).
Once in this mode, read cycles from addresses
shown in Appendix H retrieve the specified
information. To return to read array mode, write the
Read Array command (FFH).
3.4.2
PROGRAMMING THE PROTECTION
REGISTER
The protection register bits are programmed using
the two-cycle Protection Program command. The
64-bit number is programmed 16 bits at a time for
word-wide parts and eight bits at a time for byte-
wide parts. First write the Protection Program Setup
command, C0H. The next write to the device will
latch in address and data and program the specified
location. The allowable addresses are shown in
Appendix H. See Figure 17 for the Protection
Register Programming Flowchart.
PRODUCT PREVIEW
21
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