FDC37N869 Ver la hoja de datos (PDF) - SMSC -> Microchip

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componentes Descripción

Fabricante

FDC37N869

5V and 3.3V Super I/O Controller with Infrared Support for Portable Applications

SMSC -> Microchip 

TQFP

PIN #

NAME

18 14.318 MHz

Input Clock

23 IR Receive 2

SYMBOL

CLK14

IRRX2

BUFFER

MODE6

DESCRIPTION

ALTERNATE IR PINS/MISC

ICLK The external connection to a single source 14.318

MHz clock.

IS

IR Receive input

24 IR Transmit 2 IRTX2

(Note 5)

92 Address X/ nADRX/

PCI Clock nCLKRU

Controller N

21 IR Mode/ IR IRMODE/

Receive 3

IRRX3

56 Power Good/ PWRGD

nGame Port

Chip Select

nGAMEC

S

96 External

Interrupt

Input

13,70 Power

4,45, Ground

65,93

IRQIN

VCC

VSS

O12PD IR transmit output

OD12/

IOD12

O6/IS

The active-low address decoder output nADRX can

be asserted on 1, 8, or 16-byte address

boundaries (an external pull-up is required). Refer

to configuration registers CR03, CR08, and CR09

for more information. nCLKRUN is used to

indicate the PCI clock status and to request that a

stopped clock be started.

IR mode

IR Receive 3

I/O4 This active high input indicates that the power

(VCC) is valid. For device operation PWRGD must

be active. When PWRGD is inactive, all inputs are

disconnected and put into a low power mode; all

outputs are put into high impedance. The contents

of all registers are preserved as long as VCC is

valid. The output driver current drain when

PWRGD is inactive mode drops to ISTBY - standby

current.

This is the Game Port Chip Select output - active

low. It will go active when the I/O address, qualified

by AEN, matches that selected in Configuration

register CR1E.

IS

This pin is used to steer an interrupt signal from

an external device onto one of 15 IRQs.

POWER INTERFACE

Positive Supply Voltage. (5V or 3.3V)

Ground Supply.

Note 1:

Note 2:

Note 3:

Note 4:

Note 5:

Note 6:

nRI and the UART interrupts are active when PWRGD is active and the UARTS are either fully powered

or in AUTOPOWER DOWN mode.

The FDD output pins multiplexed in the PARALLEL PORT INTERFACE are OD drivers only and are not

affected by the FDD Output Driver Controls (see section CR05 on page 108).

Active (push-pull) output drivers are required on these pins in the enhanced parallel port

modes.

An external pull-up must be provided for IOCHRDY.

The pull-down on this pin is always active including when the output driver is tristated and regardless of

the state of PWRGD.

Buffer Modes describe the pad driver properties per function. Buffer Modes on multiplexed pins are

separated by a slash “/”. For example, the Buffer Modes for a multiplexed pin with two functions where

the primary function is an input and the secondary function is an 8mA bidirectional driver is “I/IO8”.

Buffer Modes in parenthesis represent multiple Buffer Modes for a single pin function.

SMSC DS – FDC37N869

Page 14

Rev. 11/09/2000

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