EM73201 Ver la hoja de datos (PDF) - ELAN Microelectronics
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EM73201 Datasheet PDF : 30 Pages
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EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
Preliminary
fc/217
WDT counter
0123
counter clear request WDT control
F/F
RQ RESET pin
system reset S
P21
WDT
command port
P21 is the control port of watch-dog-timer, and the WDT time up signal is connected to reset pin, user can
use this time up signal (active low) to reset CPU and initialize system.
P21 3 2 1 0
CWC * * WDT
initial value :0000
Program example:
CWC
0
1
Clear watch-dog-timer counter
Clear counter then return to 1
Nothing
WDT
0
1
Set watch-dog-timer
detect time
3 x 217 /fc
7 x 217 /fc
System clock frequency
4MHz 32KHz
98ms
229ms
12sec
28sec
To clear WDT with 7 x 217/fc detection time.
LDIA #0001B;
OUTA P21
; set WDT detection time and clear WDT counter
:
:
RESETTING FUNCTION
When CPU in normal working condition and RESET pin holds in low level for three instruction cycles
at least, then CPU begins to initialize the whole internal states, and when RESET pin changes to high
level, CPU begins to work in normal condition.
The CPU internal state during reset condition is as following table :
Hardware condition in RESET state
Program counter
Status flag
Interrupt enable flip-flop ( EI )
MASK0 ,1, 2, 3
Interrupt latch(IL)
P4, P5, P16, P25, P28
P1, P7, P8
XIN
Initial value
000h
01h
00h
00h
00h
00h
0Fh
Start oscillation
* This specification are subject to be changed without notice.
7.20.1999 19
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