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28F160F3

FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT

Intel 

FAST BOOT BLOCK DATASHEET

E

Table 5. Status Register Definition

WSMS

ESS

ES

PS

VPPS

PSS

DPS

R

7

6

5

4

3

2

1

0

NOTES:

SR.7 = WRITE STATE MACHINE STATUS (WSMS)

1 = Ready

0 = Busy

Check SR.7 to determine block erase or program

completion. SR.6–0 are invalid while SR.7 = “0.”

SR.6 = ERASE SUSPEND STATUS (ESS)

1 = Block Erase Suspended

0 = Block Erase in Progress/Completed

When an Erase Suspend command is issued, the

WSM halts execution and sets both SR.7 and SR.6

to “1.” SR.6 remains set until an Erase Resume

command is written to the CUI.

SR.5 = ERASE STATUS (ES)

1 = Error in Block Erasure

0 = Successful Block Erase

If both SR.5 and SR.4 are “1”s after a block erase or

program attempt, an improper command sequence

was entered.

SR.4 = PROGRAM STATUS (PS)

1 = Error in Program

0 = Successful Program

SR.3 = VPP STATUS (VPPS)

1 = VPP Low Detect, Operation Abort

0 = VPP OK

SR.3 does not provide a continuous VPP feedback.

The WSM interrogates and indicates the VPP level

only after a block erase or program operation. SR.3

is not guaranteed to reports accurate feedback

when VPP ≠ VPPH1/2 or VPPLK.

SR.2 = PROGRAM SUSPEND STATUS (PSS)

1 = Program Suspended

0 = Program in Progress/Completed

When an Program Suspend command is issued, the

WSM halts execution and sets both SR.7 and SR.2

to “1.” SR.2 remains set until an Program Resume

command is written to the CUI.

SR.1 = DEVICE PROTECT STATUS (DPS)

1 = Block Erase or Program Attempted on a

Locked Block, Operation Abort

0 = Unlocked

If a block erase or program operation is attempted to

a locked block, SR.1 is set by the WSM and aborts

the operation if WP# = VIL.

SR.0 = RESERVED FOR FUTURE

ENHANCEMENTS (R)

SR.0 is reserved for future use and should be

masked out when polling the status register.

16

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