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Vishay Semiconductors
iil410_08
ITRMS=f(TPIN5), RthJ–PIN5=16.5 K/W
Thermocouple measurement must
be performed potentially separated
to A1 and A2. Measuring junction
as near as possible at the case.
Figure 8. Current Reduction
tgd=f (IFIFT25°C), VD=200 V,
f=40 to 60 Hz, parameter: Tj
iil410_09
Figure 9. Typical Trigger Delay Time
40 to 60 Hz
line operation,
Ptot=f(ITRMS)
iil410_11
Figure 11. Power Dissipation 40 to 60 Hz Line Operation
iil410_12
VDINHmin=f(IF/IFT25°C),
parameter: Tj
Device zero voltage
switch can be triggered
only in hatched area
below Tj curves.
Figure 12. Typical Static Inhibit Voltage Limit
iil410_10
IDINH =f (IF/IFT25°C),
VD=600 V, parameter: Tj
Figure 10. Typical Inhibit Current
1
6
2
5
0.1 µF
220 V~
3
4
iil410_13
Figure 13. 1- Apply a Capacitor to the Supply Pins at the Load-Side
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6
Document Number 83690
Rev. 1.4, 10-Jan-05