AS29LV800B-70SIB Ver la hoja de datos (PDF) - ANADIGICS

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AS29LV800B-70SIB

3V 1M × 8/512K × 16 CMOS Flash EEPROM

ANADIGICS 

March 2001

AS29LV800

AC test conditions

Device under test

®

1N3064

or equivalent

+3.0V

2.7KΩ

CL*

6.2KΩ

VSS

VSS

1N3064

or equivalent

VSS

Test specifications

Test Condition

Output Load

Output Load Capacitance CL (including jig capacitance)

Input Rise and Fall Times

Input Pulse Levels

Input timing measurement reference levels

Output timing measurement reference levels

-70R,-80 -90, -120

1 TTL gate

30

100

5

0.0-3.0

1.5

1.5

Unit

pF

ns

V

V

V

Erase and programming performance

Parameter

Sector erase and verify-1 time (excludes 00h programming

prior to erase)

Programming time

Chip programming time

Erase/program cycles*

* Erase/program cycle test is not verified on each shipped unit.

Byte

Word

Limits

Min

Typical

Max

-

1.0

15

-

10

300

-

15

360

-

7.2

27

-

100,000

-

Unit

sec

µs

µs

sec

cycles

Latchup tolerance

Parameter

Input voltage with respect to VSS on A9, OE, and RESET pin

Input voltage with respect to VSS on all DQ, address, and control pins

Current

Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.

Min

Max

Unit

-1.0

+12.0

V

-0.5

VCC+0.5 V

-100

+100

mA

3/22/01; V.1.0

Alliance Semiconductor

P. 22 of 25

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