24C64 Ver la hoja de datos (PDF) - STMicroelectronics

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componentes Descripción

Fabricante

24C64

64-Kbit serial I²C bus EEPROM

STMicroelectronics 

M24C64-W M24C64-R M24C64-F

Table 11. Cycling performance

Symbol Parameter

Test condition

Max.(1)

Unit

Ncycle

Write cycle

endurance(2)

TA ≤ 25 °C, VCC(min) < VCC < VCC(max)

TA = 85 °C, VCC(min) < VCC < VCC(max)

4,000,000 Write cycle(3)

1,200,000

1. Cycling performance for products identified by process letter K or T (previous products were specified with

1 million cycles at 25 °C)

2. The Write cycle endurance is defined by characterization and qualification. For devices embedding the

ECC functionality (see Chapter 5.1.5), the write cycle endurance is defined for group of four bytes located

at addresses [4*N, 4*N+1, 4*N+2, 4*N+3] where N is an integer.

3. A Write cycle is executed when either a Page Write, a Byte write, a Write Identification Page or a Lock

Identification Page instruction is decoded. When using the Byte Write, the Page Write or the Write

Identification Page, refer also to Section 5.1.5: ECC (Error Correction Code) and Write cycling

Table 12. Memory cell data retention

Parameter

Test condition

Min.

Unit

Data retention(1)

TA = 55 °C

200(2)

Year

1. The data retention behavior is checked in production, while the data retention limit defined in this table is

extracted from characterization and qualification results.

2. For products identified by process letter K or T (previous products were specified with a data retention of 40

years at 55°C).

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