STV-5410-6500-E01 Ver la hoja de datos (PDF) - Vision

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STV-5410-6500-E01

Mono and Colour Digital Video CMOS Image Sensors

Vision 

CMOS Sensor; Customer Datasheet, Rev 3.0, 28 September 2000

VV5410 & VV6410

6. Exposure Control

6.1 Calculating Exposure Period

The exposure time, comprising coarse and fine components, for a pixel and the analogue gain are programmable via the serial

interface.

The coarse exposure value sets the number of complete lines a pixel exposes for, while the fine exposure sets the number of

additional pixel clock cycles a pixel integrates for. The sum of the two gives the overall exposure time for the pixel array.

Exposure Time = ((Coarse setting x Line Period) + (Fine setting)) x (CLKI clock period) x Clock Divider Rationote1

note1: Clock Divider Ratio = 1/(Basic Clock Division * Optional Pixel Clock Divisor)

Default Clock Divider Ratio as follows: (Optional Pixel Clock Divisor = 1)

• PAL/NTSC - 1/2

• CIF - 1/4

• QCIF - 1/8

The maximum coarse and fine exposure settings are a function of the field and line lengths respectively. The maximum coarse

exposure is current field length - 1 and the maximum fine exposure is current line length - fixed offset, see below. If an exposure

value is requested that is beyond the maximum then the applied exposure setting will be clipped to the current maximum.

Video Mode

Fine Exposure Offset (pck’s)

NTSC

51

PAL

86

CIF

51

QCIF

23

Table 6 : Fine Exposure Offset

The current revision of VV5410/VV6410 in the following modes of operation:

VP3 mode (OFF), QCIF and PAL (Video mode)

has an error in the application of coarse exposure. Please contact STMicroelectronics for more details.

6.2 Gain Components

The analogue gain in VV5410/VV6410 is programmed via the 8 bit gain register[36]. The analogue gain comprises 2

components, capacitive gain, (set by the ms nibble), and current gain, (set by the ls nibble). It is strongly recommended that the

capacitive gain setting is left at the default value of 4’b1111. Table 7 details the available gain settings in 9bit, (PAL or NTSC),

and 10bit, (CIF or QCIF), modes. We assume that mode_select[24], bit1 is 0. gain[7:0] is the value programmed in register[36].

The ls nibble of the gain value is limited to 4’he, with 4’hf not permitted.

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