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GL600USB Ver la hoja de datos (PDF) - Genesys Logic

Número de pieza
componentes Descripción
Fabricante
GL600USB
Genesys-Logic
Genesys Logic Genesys-Logic
GL600USB Datasheet PDF : 38 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
GL600USB/GL600USB-A/GL600USB-B
Value on POR: “- - 0 - - 0 0 0”
INDAR: (Address 04h/84h, Indirect address register)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
INDAR7 INDAR6 INDAR5 INDAR4 INDAR3 INDAR2 INDAR1 INDAR0
Any instruction using the INDF register actually accesses the register pointed by the INDAR register.
Value on POR: “x x x x x x x x” [1]
Note 1: “x” means unknown
PORT1 (Address 06h, Port 1 data register)
R/W
R/W
R/W
R/W
R/W
PORT1.4 PORT1.3 PORT1.2 PORT1.1 PORT1.0
PORT1 is a 5-bits latch for Port 1.0~Port 1.4. Reading the PORT1 register gets the status of the pins.
Writing to it will write to the port latch. All write operations are read-modify-write operations.
PORT1CON is used to enable/disable every bits of the port latch.
Value on POR: “- - - x x x x x”
PORT2 (Address 07h, Port 2 data register)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PORT2.7 PORT2.6 PORT2.5 PORT2.4 PORT2.3 PORT2.2 PORT2.1 PORT2.0
PORT2 is an 8-bits latch for Port 2.0~Port 2.7. Reading the PORT2 register reads the status of the pins.
Writing to it will write to the port latch. All write operations are read-modify-write operations.
PORT2CON is used to enable/disable every bits of the port latch.
Value on POR: “x x x x x x x x”
PCHBUF (Address 0Ah/8Ah, Write buffer of Program Counter’s bit 10-8)
R/W
R/W
R/W
PCHBUF2 PCHBUF1 PCHBUF0
Write buffer for upper 3-bits of Program Counter. The upper byte of Program Counter is not directly
accessible. PCHBUF is a holding register for the PC[10:8] that are transferred to the upper byte of the
Program Counter when branch occur. Please see PCL register to get more detail information.
Value on POR: “- - - - - 0 0 0”
INTEN (Address 0Bh/8Bh, Interrupt enable register)
R/W
R/W
R/W
GIE
TMROEN
TMROF
GIE: Global interrupt enable bit
1: Enable all interrupts
0: Disable all interrupts
TMROEN: Timer overflow interrupt enable bit
1: Enable timer interrupt
0: Disable timer interrupt
TMROF: Timer overflow interrupt flag bit. This bit should be cleared to ‘0’ by firmware after it is set by
hardware.
1: Timer register has overflowed
0: Timer register did not overflow
Value on POR: “0 - 0 - - 0 - -“
PHVAL (Address 0Dh, Photo-sensor value register)
R/O
R/O
R/O
R/O
PHVAL3 PHVAL2 PHVAL1 PHVAL0
PHVAL[3:0]: the 8 channel, 4 bits analog-to-digital converter data. The ADC input is select by PHSEL
register from Port 2.0~Port 2.7
16
06/19/2000
Revision 1.3

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