GL600USB Ver la hoja de datos (PDF) - Genesys Logic
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Fabricante
GL600USB Datasheet PDF : 38 Pages
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GL600USB/GL600USB-A/GL600USB-B
1: Endpoint 0 FIFO data are ready to be transmitted. Data will be transmitted when a valid IN
token is received. This bit is automatically cleared by hardware after the transaction complete
(ACK is received).
0: Endpoint 0 FIFO data are not ready to be transmitted and respond with a NAK to a valid IN
transaction.
Value on POR: “- 0 0 0 0 0 0 0”
Note 1: “W/O” means write-only bit. 0 will be returned when reading this bit
FFDAT0 (Address 17h, Endpoint 0 FIFO port)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FFDAT7 FFDAT6 FFDAT5 FFDAT4 FFDAT3 FFDAT2 FFDAT1 FFDAT0
Endpoint 0 FIFO data port
Endpoint 0 FIFO is a 8 bytes FIFO. Firmware can read/write this port 8 times to get/put the FIFO
data.
Value on POR: “x x x x x x x x”
FFDAT1 (Address 18h, Endpoint 1 FIFO port)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FFDAT7 FFDAT6 FFDAT5 FFDAT4 FFDAT3 FFDAT2 FFDAT1 FFDAT0
Endpoint 1 FIFO data port
Endpoint 1 FIFO is 8 bytes FIFO. Firmware can read this port 8 times to get the FIFO data.
Value on POR: “x x x x x x x x”
EP0RXST (Address 19h, Endpoint 0 receiving status register)
R/O
R/O
R/O
R/O
RXST3
RXST2
RXST1
RXST0
RXST[3:0]: If EP0RX is set, then there’s a complete transaction. RXST[3:0] indicate the packet received.
Bit Value
Packet received
1001
SETUP token with DATA0 packet
0101
OUT token with DATA0 packet
0110
OUT token with DATA1 packet
Value on POR: “- - - - x x x x”
4.3 MCU FUNCTION REGISTERS
Address
00h
01h
02h
03h
04h
06h
07h
0Ah
0Bh
0Dh
0Eh
0Fh
80h
81h
Name
INDR
TIMER
PCL
STATUS
INDAR
PORT1
PORT2
PCHBUF
INTEN
PHVAL
PHSEL
DMODE
INDR
PSCON
Function
Addressing this location will use the content of INDAR to address data
memory (not a physical address)
Timer register
Program Counter’s low byte
Status register
Indirect address register
Port 1 data register
Port 2 data register
Write buffer of Program Counter’s bit 10-8
Interrupt enable register
Photo-sensor value register
Photo-sensor input select register
Photo-sensor input mode register
Addressing this location will use the content of INDAR to address data
memory (not a physical address)
Prescaler control register
14
06/19/2000
Revision 1.3
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