GL602USB Ver la hoja de datos (PDF) - Genesys Logic
Número de pieza
componentes Descripción
Fabricante
GL602USB Datasheet PDF : 35 Pages
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R/W
R/W
R/W
R/W
PSDIS
PS2
PS1
PS0
PSDIS: Prescaler disable bit
1: Set prescaler disable
0: Set prescaler enable
PS[2:0]: Prescaler rate select bits. These bits are used to control timer speed. The following table means that how
many instruction cycles the TIMER register should be added by 1 when PSDIS = 0.
Bit Value Timer Rate
(PSDIS = 0)
000
1:2
001
1:4
010
1:8
011
1:16
100
1:32
101
1:64
110
1:128
111
1:256
Value on POR: “- - - - 1 1 1 1”
PORT1CON (Address 86h, Port 1 direction control register)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P1CON7 P1CON6 P1CON5 P1CON4 P1CON3 P1CON2 P1CON1
There is a data direction control bit to match every pin of Port 1. The direction control bits can configure these pins as
output or input. Setting a PORT1CON register bit put the corresponding output driver in a hi-impedance mode.
Clearing a bit in the PORT1CON register puts the contents of the output latch on the selected pin.
Value on POR: “1 1 1 1 1 1 1 -”
4.4 GENERAL PURPOSE I/O PORTS
Interface with peripherals is conducted via up to 7 GPIO signals. The 7 signals are located at port 1. The port 1 data
register is located at data memory address 06h and direction control register is located at address 86h.
The GL602USB builds in a PS/2 host data receiver. While this receiver enabled, the Port 1.1 is treated as PS/2 CLK
and Port 1.2 is treated as PS/2 DATA. Firmware uses these 2 pins to implement a PS/2 mouse host controller. When
the PS/2 host want to send command to PS/2 device, firmware should drive the 2 I/O pins directly following PS/2
specification.
There are 2 bytes FIFO used as PS/2 data buffer. When the PS/2 receiver has received a data byte already and
firmware does not read it yet, the PS/2 receiver can receive the next data byte into FIFO still. If the firmware cannot
process the first byte until the second byte received complete, the PS/2 receiver will drive low on Port 1.1 (PS/2 CLK)
automatically to avoid the PS/2 device send data again.
P1.3 is VPP pin at OTP. This I/O pin can be used only at mask type.
The Port 1.5/Port 1.6/Port 1.7 can be treat as general purpose output pins in output mode. There are internal pull up
resistors on those pins. Firmware can drive high on these pins to turn off LEDs and drive low to turn off these pins.
External resistors are needed for these LED pins to sink current .
4.5 TIMER INTERRUPT
The Timer Interrupt is generated when the TIMER register overflows from FFh to 00h. This overflow sets bit TMROF
(INTEN<2>). The interrupt can be masked by clearing bit TMROEN (INTEN<5>). Bit TMROF must be cleared in
software by the Timer module interrupt service routine otherwise the Timer Interrupt will not be generated again. If
prescaler is disabled, the timer register will increase every instruction cycle. If prescaler is enabled, its increment cycle
depends on PS0~PS2 bits in PSCON register.
Revision 1.6
-18-
02/28/2000
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