GL602USB Ver la hoja de datos (PDF) - Genesys Logic
Número de pieza
componentes Descripción
Fabricante
GL602USB Datasheet PDF : 35 Pages
| |||
STATUS (Address 03h, Status register)
R/W
R/W
R/W
R/W
BS
ZO
HC
CA
BS: Bank Select. Because only 7 bits (bit 0~bit 6) operand implied by instruction for register address, this bit is used
as address bit 7 when register access.
1: Bank 1 (80h-FFh)
0: Bank 0 (00h-7Fh)
ZO: Zero bit
1: The result of last arithmetic or logic operation is zero
0: The result of last arithmetic or logic operation is not zero
HC: Half Carry/Borrow bit
1: Carry or not borrow from the 4th low order bit
0: Borrow or not carry from the 4th low order bit
CA: Carry/Borrow bit
1: Carry or not borrow from the most significant bit
0: Borrow or not carry from the most significant bit
Value on POR: “- - 0 - - 0 0 0”
INDAR: (Address 04h/84h, Indirect address register)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
INDAR7 INDAR6 INDAR5 INDAR4 INDAR3 INDAR2 INDAR1 INDAR0
Any instruction using the INDF register actually accesses the register pointed by the INDAR register.
Value on POR: “x x x x x x x x” [1]
Note 1: “x” means unknown
PORT1 (Address 06h, Port 1 data register)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PORT 1.7 PORT1.6 PORT1.5 PORT1.4 PORT1.3 PORT1.2 PORT1.1
PORT1 is a 7-bits latch for Port 1.1~Port 1.7. Reading the PORT1 register gets the status on the pins. Writing to it will
write to the port latch. All write operations are read-modify-write operations. PORT1CON is used to enable/disable
every bits of the port latch.
Value on POR: “x x x x x x x -”
PCHBUF (Address 0Ah/8Ah, Write buffer of Program Counter’s bit 11-8)
R/W
R/W
R/W
R/W
PCHBUF3 PCHBUF2 PCHBUF1 PCHBUF0
Write buffer for upper 4-bits of Program Counter. The upper byte of Program Counter is not directly accessible.
PCHBUF is a holding register for the PC[11:8] that are transferred to the upper byte of the Program Counter when
branch occur. Please see PCL register to get more detail information.
Value on POR: “- - - 0 0 0 0 0”
INTEN (Address 0Bh/8Bh, Interrupt enable register)
R/W
R/W
R/W
GIE
TMROEN
TMROF
GIE: Global interrupt enable bit
1: Enable all interrupts
0: Disable all interrupts
TMROEN: Timer overflow interrupt enable bit
1: Enable timer interrupt
0: Disable timer interrupt
TMROF: Timer overflow interrupt flag bit. This bit should be cleared to ‘0’ by firmware after it is set by hardware.
1: Timer register has overflowed
0: Timer register did not overflow
Value on POR: “0 - 0 - - 0 - -“
PSCON (Address 81h, Prescaler control register)
Revision 1.6
-17-
02/28/2000
Share Link: 