GL602USB Ver la hoja de datos (PDF) - Genesys Logic
Número de pieza
componentes Descripción
Fabricante
GL602USB Datasheet PDF : 35 Pages
| |||
4.3 MCU FUNCTION REGISTERS
Address
00h
01h
02h
03h
04h
05h
06h
0Ah
0Bh
80h
81h
82h
83h
84h
85h
86h
8Ah
8Bh
Name
INDR
TIMER
PCL
STATUS
INDAR
Reserved
PORT1
PCHBUF
INTEN
INDR
PSCON
PCL
STATUS
INDAR
Reserved
PORT1CON
PCHBUF
INTEN
Table 4-2 MCU Function Register Summary
Function
Addressing this location will use the content of INDAR to address data
memory (not a physical address)
Timer register
Program Counter’s low byte
Status register
Indirect address register
Port 1 data register
Write buffer of Program Counter’s bit 11-8
Interrupt enable register
Addressing this location will use the content of INDAR to address data
memory (not a physical address)
Prescaler control register
Program Counter’s low byte
Status register
Indirect address register
Port 1 direction control register
Write buffer of Program Counter’s bit 12-8
Interrupt enable register
INDR (Address 00h/80h)
INDR is not a physical register. Addressing INDR register will cause indirect addressing. Any instruction using the
INDF register actually accesses the register pointed by the INDAR register. The indirect addressing method only can
be used for general purpose registers.
TIMER (Address 01h, Timer register)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TIMER7 TIMER6 TIMER5 TIMER4 TIMER3 TIMER2 TIMER1 TIMER0
The timer starts to count up after power on reset. The TMROF bit at INTEN register will be set when the TIMER
register overflows from FFh to 00h. If both TMROEN and GIE bits at INTEN register are set, an interrupt will be
generated when TIMER register overflows.
Value on POR: “0 0 0 0 0 0 0 0”
PCL (Address 02h/82h, Program Counter’s low byte)
R/W
R/W
R/W
R/W
PCL7
PCL6
PCL5
PCL4
R/W
PCL3
R/W
PCL2
R/W
PCL1
R/W
PCL0
The Program Counter (PC) is 12-bits wide. The low byte comes from the PCL register, which is a readable and
writable register. The high byte is not directly readable or writable and comes from PCHBUF. The GL602USB has a 8
level deep x 11-bit wide hardware stake. The stake space is not part of either program or data space and the stack
pointer is not readable or writable. The PC is pushed onto the stack when a CALL instruction is executed or an
interrupt causes a branch. The stack is poped in the event of a RETIA, RETI or a RET instruction execution. PCHBUF
is not affected by a push or pop operation.
Because branch address gotten from stack or direct from instruction is only 11 bits long, the highest bit will be loaded
to PC from PCHBUF when branch instruction is executed.
When write to PCL command executed, all 4 bits of PCHBUF will be loaded to PC because PCL is only a 8 bits
register.
Value on POR: “0 0 0 0 0 0 0 0”
Revision 1.6
-16-
02/28/2000
Share Link: 