11274-001 Ver la hoja de datos (PDF) - AMI Semiconductor
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componentes Descripción
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11274-001 Datasheet PDF : 39 Pages
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FS6131-01
Programmable Line Lock Clock Generator IC
Table 1: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active Low pin
PIN
TYPE
NAME
DESCRIPTION
1
DI
SCL
Serial Interface Clock (requires an external pull-up)
2
DIO
SDA
Serial Interface Data Input/Output (requires an external pull-up)
3
DI
ADDR
Address Select Bit (see Section 5.2.1)
4
P
VSS
Ground
5
AI
XIN
VCXO Feedback
6
AO
XOUT
VCXO Drive
7
AI
XTUNE
VCXO Tune
8
P
VDD
Power Supply (+5V)
9
DIO
LOCK/IPRG Lock Indicator / PECL Current Drive Programming
10
AI
EXTLF
External Loop Filter
11
P
VSS
Ground
12
DI
REF
Reference Frequency Input
13
DI
FBK
Feedback Input
14
P
VDD
Power Supply (+5V)
15
DO
CLKP
Differential Clock Output (+)
16
DO
CLKN
Differential Clock Output (-)
4.0 Functional Block Description
frequency appearing at the inputs of the PFD are equal.
The input/output relationship between the reference fre-
quency and the VCO frequency is
4.1 Main Loop PLL
The Main Loop Phase Locked Loop (ML-PLL) is a stan-
dard phase- and frequency- locked loop architecture. As
shown in Figure 2, the ML-PLL consists of a Reference
Divider, a Phase-Frequency Detector (PFD), a charge
pump, an internal loop filter, a Voltage-Controlled Oscil-
lator (VCO), a Feedback Divider, and a Post Divider.
During operation, the reference frequency (fREF), gener-
ated by either the on-board crystal oscillator or an exter-
nal frequency source, is first reduced by the Reference
Divider. The integer value that the frequency is divided by
is called the modulus, and is denoted as NR for the Ref-
erence Divider. The divided reference is then fed into the
PFD.
The PFD controls the frequency of the VCO (fVCO)
through the charge pump and loop filter. The VCO pro-
vides a high-speed, low noise, continuously variable fre-
quency clock source for the ML-PLL. The output of the
VCO is fed back to the PFD through the Feedback Di-
vider (the modulus is denoted by NF) to close the loop.
The PFD will drive the VCO up or down in frequency until
the divided reference frequency and the divided VCO
fVCO = fREF .
NF
NR
If the VCO frequency is used as the PLL output fre-
quency (fCLK) then the basic PLL equation can be rewrit-
ten as
fCLK
=
f REF
ççèæ
NF
NR
÷÷øö .
4.1.1 Reference Divider
The Reference Divider is designed for low phase jitter.
The divider accepts either the output of either the Crystal
Loop (the VCXO output) or an external reference fre-
quency, and provides a divided-down frequency to the
PFD. The Reference Divider is a 12-bit divider, and can
be programmed for any modulus from 1 to 4095. See
both Table 3 and Table 8 for additional programming in-
formation.
2
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