11257-801 Ver la hoja de datos (PDF) - AMI Semiconductor

Número de pieza

componentes Descripción

Fabricante

11257-801

Low-Skew Clock Fanout Buffer ICs

AMI Semiconductor 

     X  T

)6)6)6)6

/RZ6NHZ &ORFN )DQRXW %XIIHU ,&V

April 1999

Series termination adds no dc loading to the driver, and

requires less power than other resistive termination

methods. Further, no extra impedance exists from the

signal line to a reference voltage, such as ground.

As shown in Figure 19, the sum of the driver’s output im-

pedance (zO) and the series termination resistance (RS)

must equal the line impedance (zL). That is,

RS = zL − zO .

Note that when the source impedance (zO+RS) is

matched to the line impedance, then by voltage division

the incident wave amplitude is one-half of the full signal

amplitude.

Vi

=V

(zO + RS )

(zO + RS ) + zL

=V

2

The full signal amplitude may take up to twice as long as

the propagation delay of the line to develop, reducing

noise immunity during the half-amplitude period. Note

also that the voltage at the receive end must add up to a

signal amplitude that meets the receiver switching

thresholds. The slew rate of the signal is also reduced

due to the additional RC delay of the load capacitance

and the line impedance. Also note that the output driver

impedance will vary slightly with the output logic state

(high or low).

8.2 Dynamic Power Dissipation

High-speed clock drivers require careful attention to

power dissipation. Transient power (PT) consumption can

be derived from

PT = VDD 2 × Cload × f CLK × N SW

where Cload is the load capacitance, VDD is the supply

voltage, fCLK is the clock frequency, and Nsw is the

number of switching outputs.

The internal heat (junction temperature, TJ) generated by

the power dissipation can be calculated from

TJ = Θ JA × PT + TA

where ΘJA is the package thermal resistance, TA is the

ambient temperature, and PT is derived above.

pacitance, and the number of connected devices with

their associated input currents.

Control of the clock and data lines is done through open

drain/collector current-sink outputs, and thus requires

external pull-up resistors on both lines. A guideline is

RP

<

tr

2 × Cbus

,

where tr is the maximum rise time (minus some margin)

and Cbus is the total bus capacitance. Assuming an I2C

device on each DIMM, an I2C controller, the clock buffer,

and two other bus devices results in values in the 5kΩ to

7kΩ range. Use of a series resistor to provide protection

against high voltage spikes on the bus will alter the val-

ues for RP.

Figure 20: Connections to the Serial Bus

SDA

SCL

RS

(optional)

RP

RS

(optional)

Clock Out

Data In

Data Out

TRANSMITTER

RP

RS

(optional)

RS

(optional)

Clock In

Data In

Data Out

RECEIVER

8.3.1 For More Information

More detailed information on serial bus design can be

obtained from SMBus and I2C Bus Design, available from

the Intel Corporation at http://www.intel.com.

Information on the I2C-bus can be found in the document

The I2C-bus And How To Use It (Including Specifica-

tions), available from Philips Semiconductors at

http://www-us2.semiconductors.philips.com.

Additional information on the System Management Bus

can be found in the System Management Bus Specifica-

tion, available from the Smart Battery System

Implementers’ Forum at http://www.sbs-forum.org.

8.3 Serial Communications

Connection of devices to a standard-mode implementa-

tion of either the I2C-bus or the SMBus is similar to that

shown in Figure 20. Selection of the pull-up resistors (RP)

and the optional series resistors (RS) on the SDA and

SCL lines depends on the supply voltage, the bus ca-

4.5.99

,62

19

Share Link: