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KB3930 Datasheet PDF : 199 Pages
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KB3930 Keyboard Controller Datasheet
4.1.2 Clock Domains
Three clock sources, PCICLK, DPLL_CLK and XCLKI will be discussed in this section. A
summary is list in the following table.
Clock
Description
PCICLK
PCI clock 33MHz for LPC I/F.
DPLL_CLK
Main clock for 8051/peripheral. DPLL clock can be generated with or without XCLK for
reference. DPLL clock can be divided for different applications. Fig. 4-1 gives an example for
illustration.
XCLKI
External 32.768KHz for reference.
The following figure shows more detail about the operation in the KBC. The external
32.768KHz is provided for two purposes. One is to provide an accurate reference for internal DPLL
module, and the other one is to provide another clock source for watchdog timer.
The possible (X,Y,Z) combination with exact clock value is summarized as the following table.
SPI Clock (X)
Main Clock (Y)
Peripheral Clock (Z)
CLKCFG[6]=0 CLKCFG[6]=1 CLKCFG[6]=0 CLKCFG[6]=1 CLKCFG[6]=0 CLKCFG[6]=1
(default)
(default)
(default)
CLKCFG[3:2]=0
16*
66
8*
8
4*
4
(default)
CLKCFG[3:2]=1
32
66
16
16
8
8
CLKCFG[3:2]=2
32
66
22
22
11
11
CLKCFG[3:2]=3
32
66
32
32
16
16
* While power on default, no matter what value CLKCFG[3:2], CLKCFG[6] are, the dividend (X,Y,Z) is always (4,
8, 16). The PCI clock is 66MHz, X= 66/4 = 16MHz, Y= 66/8 = 8Mhz , Z= 66/16 = 4MHz
Be noted that, these clock frequency is only valid after KBC correctly referring clock.
Copyright©2010, ENE Technology Inc.
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