WM8501(2006) Ver la hoja de datos (PDF) - Wolfson Microelectronics plc
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WM8501 Datasheet PDF : 20 Pages
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WM8501
MASTER CLOCK TIMING
MCLK
tMCLKL
tMCLKH
tMCLKY
Figure 1 Master Clock Timing Requirements
Test Conditions
VDD = 5V, GND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
System Clock Timing Information
MCLK Master clock pulse width high
MCLK Master clock pulse width low
MCLK Master clock cycle time
tMCLKH
tMCLKL
tMCLKY
MCLK Duty cycle
Time from MCLK stopping to power
down.
TEST CONDITIONS
MIN
8
8
20
40:60
1.5
DIGITAL AUDIO INTERFACE
Pre-Production
TYP
MAX
UNIT
ns
ns
ns
60:40
12
µs
Figure 2 Digital Audio Data Timing
Test Conditions
VDD = 5V, GND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
Audio Data Input Timing Information
BCLK cycle time
tBCY
40
BCLK pulse width high
tBCH
16
BCLK pulse width low
tBCL
16
LRCLK set-up time to BCLK
tLRSU
8
rising edge
LRCLK hold time from
tLRH
8
BCLK rising edge
DIN set-up time to BCLK
tDS
8
rising edge
DIN hold time from BCLK
tDH
8
rising edge
w
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
PP Rev 3.1 May 2006
8
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