WM8501(2006) Ver la hoja de datos (PDF) - Wolfson Microelectronics plc
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WM8501 Datasheet PDF : 20 Pages
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WM8501
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
Analogue supply range
AVDD
4.5
Digital supply range
DVDD
2.7
Ground
AGND, DGND
Analog supply current
AVDD = 5V
Digital supply current
DVDD = 5V
DVDD = 3.3V
Power down current (note 4)
AVDD=DVDD=5V
TYP
0
9
8
4.5
0.01
Pre-Production
MAX
5.5
5.5
UNIT
V
V
V
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD = 5V, DVDD = 3.3V, GND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL TEST CONDITIONS
MIN
TYP
MAX
Digital Logic Levels (TTL Levels)
Input LOW level
VIL
0.8
Input HIGH level
VIH
2.0
Output LOW
VOL
IOL = 2mA
DGND + 0.3V
Output HIGH
VOH
IOH = 2mA
DVDD – 0.3V
Analogue Reference Levels
Reference voltage (VMID)
AVDD/2
Potential divider resistance
RCAP
AVDD to VMID and
50
VMID to GND
DAC Output (Load = 10kΩ. 50pF)
0dBFs Full scale output voltage
At DAC outputs
1.6 x
AVDD/5
1.7 x
AVDD/5
1.8 x
AVDD/5
Signal to Noise Ratio (Note
5,6,7)
SNR
A-weighted,
90
100
@ fs = 48kHz
A-weighted
97
@ fs = 96kHz
A-weighted
97
@ fs = 192kHz
Dynamic Range (Note 2, 6)
DNR
A-weighted, -60dB full
90
100
scale input
Total Harmonic Distortion
(Note 7)
THD
1kHz, Load = 10kΩ,
0dBFS
-88
-78
DAC channel separation
93
Analogue Output Levels
Output level
Load = 10kΩ, 0dBFS
1.7
Gain mismatch
±1
channel-to-channel
Minimum resistance load
To midrail or a.c.
16
coupled
Output d.c. level
AVDD/2
UNIT
V
V
V
V
V
kΩ
Vrms
dB
dB
dB
dB
dB
dB
Vrms
%FSR
Ω
V
Notes:
1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’ weighted
over a 20Hz to 20kHz bandwidth.
2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a
filter will result in higher THD and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics.
The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values.
3. VMID pin decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).
4. Power down occurs 1.5µs after MCLK is stopped.
w
PP Rev 3.1 May 2006
6
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