INIC-1511 Ver la hoja de datos (PDF) - Unspecified
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INIC-1511 Datasheet PDF : 26 Pages
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INIC-1511 (Preliminary)
7. Host poll bit 7 of I2C_Comm(0x40E3) until this bit is cleared by sending DATA_READ packet
with wValue I2C_Comm(0x40BF)
8. Host send DATA_READ packet with wValue I2C_Status(0x40E4) to check write success or not
4.5.2 NVRAM Read.
9. Host send DATA_WRITE packet with wValue I2C_Addr(0x40E0) and wIndex[15:8] the
NVRAM address to be accessed
10. Host send DATA_WRITE packet with wValue I2C_Ctrl(0x40E2) and wIndex[15:8] the Control
Code to be write to NVRAM
11. Host send DATA_WRITE packet with wValue I2C_Comm(0x40E3) and wIndex[15:8] the Run
bit[b7] and read/write direction 1 [b0]
12. Host poll bit 7 of I2C_Comm(0x40E3) until this bit is cleared by sending DATA_READ packet
with wValue I2C_Comm(0x40E3)
13. Host send DATA_READ packet with wValue I2C_Data(0x40E1) to get the data from NVRAM.
14. Host send DATA_READ packet with wValue I2C_Status(0x40E4) to check write success or not
4.5.3 NVRAM Polling.
Same as NVRAM Read. If I2C_Status(0x40E4) bit 0 is 1, NVRAM not ready for next write.
5. Register Address Mapping:
5.1 USB Block (address area: 60xx)
Address
20h
21h
22h
25h
26h
30h
31h
32h
33h
34h
38-3F
40h
41h
50h
51h
52h
53h
60h
61h
70h
71h
72h
73h
74h
80h
81h
82h
83h
Read Value
Dev_Status
Funct_Adr
Test_mode
EpTxLength[7:0]
EpTxLength[15:8]
EP0_Status
EP0_Status
EP0_Status2
EP0_Status2
EP0TxLength
Hdr0-7
EP1_Status
EP1_Status
EP2_Status
EP2_Status
Usb_rxLength[7:0]
Usb_rxlength[15:8]
EP3_Status
EP3_Status
TotalCnt0
TotalCnt1
TotalCnt2
TotalCnt3
-
GTotalCnt0
GTotalCnt1
GTotalCnt2
GTotalCnt3
Write Value
Dev_Status
Funct_Adr
Test_mode
EpTxLength[7:0]
EpTxLength[15:8]
EP0_ Control (Set)
EP0_ Control (Clear)
EP0_ Control 2(Set)
EP0_ Control 2(Clear)
EP0TxLength
-
EP1_ Control (Set)
EP1_ Control (Clear)
EP2_ Control (Set)
EP2_ Control (Clear)
-
-
EP3_ Control (Set)
EP3_ Control (Clear)
TotalCnt0
TotalCnt1
TotalCnt2
TotalCnt3
LoadTotalCnt
GTotalCnt0
GTotalCnt1
GTotalCnt2
GTotalCnt3
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