RTL8111E Ver la hoja de datos (PDF) - Realtek Semiconductor

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RTL8111E

INTEGRATED GIGABIT ETHERNET CONTROLLER FOR PCI EXPRESS APPLICATIONS

Realtek Semiconductor 

RTL8111E

Datasheet

Symbol

Parameter

100MHz Input

Units Note

Min

Max

Duty Cycle

Duty Cycle

40

60

%

2

Rise-Fall Matching Rising Edge Rate (REFCLK+) to

-

20

%

1, 14

Falling Edge Rate (REFCLK-) Matching

ZC-DC

Clock Source DC Impedance

40

60

Ω

1, 11

Note1: Measurement taken from single-ended waveform.

Note2: Measurement taken from differential waveform.

Note3: Measured from -150mV to +150mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The

signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is

centered on the differential zero crossing. See Figure 10, page 31.

Note4: Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the

falling edge of REFCLK-. See Figure 7, page 30.

Note5: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing.

Refers to all crossing points for this measurement. See Figure 7, page 30.

Note6: Defines as the absolute minimum or maximum instantaneous period. This includes cycle to cycle jitter, relative

ppm tolerance, and spread spectrum modulation. See Figure 9, page 30.

Note7: Defined as the maximum instantaneous voltage including overshoot. See Figure 7, page 30.

Note8: Defined as the minimum instantaneous voltage including undershoot. See Figure 7, page 30.

Note9: Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the

maximum allowed variance in VCROSS for any particular system. See Figure 7, page 30.

Note10: Refer to Section 4.3.2.1 of the PCI Express Base Specification, Revision 1.1 for information regarding ppm

considerations.

Note11: System board compliance measurements must use the test load card described in Figure 13, page 32. REFCLK+

and REFCLK- are to be measured at the load capacitors CL. Single ended probes must be used for measurements

requiring single ended measurements. Either single ended probes with math or differential probe can be used for

differential measurements. Test load CL=2pF.

Note12: TSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after

rising/falling edges before it is allowed to droop back into the VRB ±100mV differential range. See Figure 12, page 31.

Note13: PPM refers to parts per million and is a DC absolute period accuracy specification. 1ppm is 1/1,000,000th of

100.000000MHz exactly, or 100Hz. For 300ppm then we have an error budget of 100Hz/ppm*300ppm=30kHz. The

period is to be measured with a frequency counter with measurement window set to 100ms or greater. The ±300ppm

applies to systems that do not employ Spread Spectrum or that use common clock source. For systems employing Spread

Spectrum there is an additional 2500ppm nominal shift in maximum period resulting from the 0.5% down spread resulting

in a maximum average period specification of +2800ppm.

Note14: Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a

±75mV window centered on the median cross point where REFCLK+ rising meets REFCLK- falling. The median cross

point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge

Rate of REFCLK+ should be compared to the Fall Edge Rate of REFCLK-; the maximum allowed difference should not

exceed 20% of the slowest edge rate. See Figure 8, page 30.

Note15: Refer to PCI Express Card Electromechanical Specification, rev.1.1, for correct measurement environment

setting of each parameter.

Integrated Gigabit Ethernet Controller for PCI Express

29

Track ID: JATR-2265-11 Rev. 1.5

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