RTL8111E Ver la hoja de datos (PDF) - Realtek Semiconductor

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RTL8111E

INTEGRATED GIGABIT ETHERNET CONTROLLER FOR PCI EXPRESS APPLICATIONS

Realtek Semiconductor 

RTL8111E

Datasheet

The corresponding wake-up method (message or LANWAKEB) is asserted only when the following

conditions are met:

• The PMEn bit (bit0, CONFIG1) is set to 1.

• The PME_En bit (bit8, PMCSR) in PCI Configuration Space is set to 1.

• The RTL8111E may assert the corresponding wake-up method (message or LANWAKEB) in the

current power state or in isolation state, depending on the PME_Support (bit15~11) setting of the

PMC register in PCI Configuration Space.

• A Magic Packet, LinkUp, or Wakeup Frame has been received.

• Writing a 1 to the PME_Status (bit15) of the PMCSR register in the PCI Configuration Space clears

this bit and causes the RTL8111E to stop asserting the corresponding wake-up method (message or

LANWAKEB) (if enabled).

When the RTL8111E is in power down mode, e.g., D1~D3, the IO, and MEM accesses to the RTL8111E

are disabled. After a PERSTB assertion, the device’s power state is restored to D0 automatically if the

original power state was D3cold. There is almost no hardware delay at the device’s power state transition.

When in ACPI mode, the device does not support PME (Power Management Enable) from D0 (this is the

Realtek default setting of the PMC register auto-loaded from EEPROM). The setting may be changed

from the EEPROM, if required.

6.7. Vital Product Data (VPD)

Bit 31 of the Vital Product Data (VPD) capability structure in the RTL8111E’s PCI Configuration Space

is used to issue VPD read/write commands and is also a flag used to indicate whether the transfer of data

between the VPD data register and the 93C46/93C56/93C66 has completed or not.

Write VPD register: (write data to the 93C46/93C56/93C66):

Set the flag bit to 1 at the same time the VPD address is written to write VPD data to EEPROM. When

the flag bit is reset to 0 by the RTL8111E, the VPD data (4 bytes per VPD access) has been transferred

from the VPD data register to EEPROM.

Read VPD register: (read data from the 93C46/93C56/93C66):

Reset the flag bit to 0 at the same time the VPD address is written to retrieve VPD data from EEPROM.

When the flag bit is set to 1 by the RTL8111E, the VPD data (4 bytes per VPD access) has been

transferred from EEPROM to the VPD data register.

Note1: Refer to the PCI 2.3 Specifications for further information.

Note2: The VPD address must be a DWORD-aligned address as defined in the PCI 2.3 Specifications.

VPD data is always consecutive 4-byte data starting from the VPD address specified.

Note3: Realtek reserves offset 60h to 7Fh in EEPROM mainly for VPD data to be stored.

Note4: The VPD function of the RTL8111E is designed to be able to access the full range of the

93C46/93C56/93C66 EEPROM.

Integrated Gigabit Ethernet Controller for PCI Express

17

Track ID: JATR-2265-11 Rev. 1.5

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