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IT8510TE

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IT8510E

6.2.4.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 54

6.2.4.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 54

6.2.4.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0]) ............................ 54

6.2.4.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 54

6.2.4.7 Interrupt Request Type Select (IRQTP) .................................................................. 54

6.2.5 KBC / Mouse Interface Configuration Registers .................................................................. 54

6.2.5.1 Logical Device Activate Register (LDA)................................................................... 55

6.2.5.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 55

6.2.5.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 55

6.2.5.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 55

6.2.5.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0]) ............................ 55

6.2.5.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 56

6.2.5.7 Interrupt Request Type Select (IRQTP) .................................................................. 56

6.2.6 KBC / Keyboard Interface Configuration Registers.............................................................. 56

6.2.6.1 Logical Device Activate Register (LDA)................................................................... 56

6.2.6.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 56

6.2.6.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 56

6.2.6.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 57

6.2.6.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0]) ............................ 57

6.2.6.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 57

6.2.6.7 Interrupt Request Type Select (IRQTP) .................................................................. 57

6.2.7 Shared Memory/Flash Interface (SMFI) Configuration Registers ........................................ 57

6.2.7.1 Logical Device Activate Register (LDA)................................................................... 58

6.2.7.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 58

6.2.7.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 58

6.2.7.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 58

6.2.7.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0]) ............................ 58

6.2.7.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 58

6.2.7.7 Interrupt Request Type Select (IRQTP) .................................................................. 59

6.2.7.8 Shared Memory Configuration Register (SHMC) .................................................... 59

6.2.7.9 Shared Memory Base Address High Byte Register (SHMBAH).............................. 59

6.2.7.10 Shared Memory Base Address Low Byte Register (SHMBAL) ............................... 59

6.2.7.11 Shared Memory Size Configuration Register (SHMSZ) .......................................... 60

6.2.7.12 LPC Memory Control (LPCMCTRL) ........................................................................ 60

6.2.8 Real Time Clock (RTC) Configuration Registers ................................................................. 60

6.2.8.1 Logical Device Activate Register (LDA)................................................................... 61

6.2.8.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 61

6.2.8.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 61

6.2.8.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 61

6.2.8.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0]) ............................ 62

6.2.8.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 62

6.2.8.7 Interrupt Request Type Select (IRQTP) .................................................................. 62

6.2.8.8 RAM Lock Register (RLR) ....................................................................................... 62

6.2.8.9 Date of Month Alarm Register Offset (DOMAO) ..................................................... 62

6.2.8.10 Month Alarm Register Offset (MONAO) .................................................................. 63

6.2.9 Power Management I/F Channel 1 Configuration Registers................................................ 63

6.2.9.1 Logical Device Activate Register (LDA)................................................................... 63

6.2.9.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 63

6.2.9.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 63

6.2.9.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 64

6.2.9.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0]) ............................ 64

6.2.9.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 64

6.2.9.7 Interrupt Request Type Select (IRQTP) .................................................................. 64

6.2.10 Power Management I/F Channel 2 Configuration Registers................................................ 64

6.2.10.1 Logical Device Activate Register (LDA)................................................................... 65

6.2.10.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 65

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IT8510E/TE/G V0.7.2

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