SPT2210SCT Ver la hoja de datos (PDF) - Signal Processing Technologies

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SPT2210SCT

Y/C VIDEO ENCODER

Signal Processing Technologies 

COMMAND REGISTER DESCRIPTIONS

H/V I/O REGISTER

(Address = 04H)

D4 D3 D2 D1 D0

MSB

LSB

Table XII – H/V I/O Register Description Table

Address

04H

Bit #

7-5

4

3

2

1

0

Function

Bit Setting /Description

Not used

Fix at 0

Field polarity

0 Positive logic.

High level = Odd field

1 Negative logic.

High level = Even field

V signal (VSYNC and VBLNK) polarity

0 Positive logic

1 Negative logic

H signal (HSYNC and HBLNK) polarity

0

Positive logic

1 Negative logic

Blank I/O

0 HBLNK/VBLNK/FIELD

output mode

1 HBLNK/VBLNK/FIELD

input mode

Timing I/O

0 HSYNC/VSYNC input mode

1 HBLNK/VBLNK/FIELD I/O

mode

Default

00H

H/V TIMING REGISTER

(Address = 05H)

D6 D5 D4 D3 D2 D1 D0

MSB

LSB

Table XIII – H/V Timing Register Description Table

Address Bit #

05H

7

6-5

Function

Not used

Vertical Blank timing

4-0 Horizontal Blank timing

Bit Setting /Description

Fix at 0

00 1V=240H

01 1V=241H

10 1V=242H

11 Not used

See table XIV

Default

00H

Table XIV – Horizontal Blank Timing Control (H/V Timing Register)

D4....D0

01111

01110

•

•

•

00001

00000

HBLNK Timing

+15 clocks from the original point.

+14 clocks from the original point.

•

•

•

+1 clock from the original point.

+0 (Default: original point)

D4....D0

10001

10010

•

•

•

11110

11111

HBLNK Timing

–1 clock from the original point.

–2 clocks from the original point.

•

•

•

–14 clocks from the original point.

–15 clocks from the original point.

SPT

SPT2210

13

8/22/00

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