HFA3841 Ver la hoja de datos (PDF) - Intersil

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HFA3841

Wireless LAN Medium Access Controller

Intersil 

Preliminary - HFA3841

Buffer Access Paths

The HFA3841 has two independent buffer access paths,

which permits concurrent read and write transfers. The

firmware provides dynamic memory allocation between

Transmit and Receive, allowing efficient memory utilization.

On-the-fly allocation of (128-byte) memory blocks as needed

for reception wastes minimal space when receiving

fragments. The HFA3841 hides management of free

memory from the driver, and allows fast response and

minimum data copying for low latency. The firmware

provides direct access to TX and RX buffers based on

Frame ID (FID). This facilitates Power Management queuing,

and allows dynamic fragmentation and defragmentation by

controller. Simple Allocate/Deallocate commands insure low

host CPU overhead for memory management.

Hardware buffer chaining provides high performance while

reading and writing buffers. Data is transferred between the

host driver and the HFA3841 by writing or reading a single

register location (The Buffer Access Path, or BAP). Each

access increments the address in the buffer memory.

Internally, the firmware allocates blocks of memory as

needed to provide the requested buffer size. These blocks

may not be contiguous, but the firmware builds a linked list of

pointers between them. When the host driver is transferring

data through a buffer access path and reaches the end of a

physical memory block, hardware in the host interface

follows the linked list so that the buffer access path points to

the beginning of the next memory block. This process is

completely transparent to the host driver, which simply

writes or reads all buffer data to the same register. If the host

driver attempts to access beyond the end of the allocated

buffer, subsequent writes are ignored, and reads will be

undefined.

FID

BUFFER DESCRIPTOR

ACCESS (FIRMWARE)

ALLOCATE/

DEALLOCATE

REQUEST

OFFSET CENTER

BLOCK

A

OFFSET

VIRTUAL

FRAME BUFFER

STATUS

HEADER

HOST

BUS

DATA PORT

PRE-READ/

POST-WRITE

D

DATA

BUFFER

MEMORY

FIGURE 15. BLOCK DIAGRAM OF A BUFFER ACCESS PATH

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