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AD650KP

Voltage-to-Frequency and Frequency-to-Voltage Converter

Analog Devices 

AD650

12 inches of 20 gauge wire will produce a voltage spike of 50 mV.

The separate digital ground of the AD650 will easily handle

these types of switching transients.

A problem will remain from interference caused by radiation of

electro-magnetic energy from these fast transients. Typically, a

voltage spike is produced by inductive switching transients;

these spikes can capacitively couple into other sections of the

circuit. Another problem is ringing of ground lines and power

supply lines due to the distributed capacitance and inductance

of the wires. Such ringing can also couple interference into sen-

sitive analog circuits. The best solution to these problems is

proper bypassing of the logic supply at the AD650 package. A

1 µF to 10 µF tantalum capacitor should be connected directly

to the supply side of the pull-up resistor and to the digital

ground—Pin 10. The pull-up resistor should be connected di-

rectly to the frequency output—Pin 8. The lead lengths on the

bypass capacitor and the pull up resistor should be as short as

possible. The capacitor will supply (or absorb) the current tran-

sients, and large ac signals will flow in a physically small loop

through the capacitor, pull up resistor, and frequency output

transistor. It is important that the loop be physically small for

two reasons: first, there is less self-inductance if the wires are

short, and second, the loop will not radiate RFI efficiently.

The digital ground (Pin 10) should be separately connected to

the power supply ground. Note that the leads to the digital

power supply are only carrying dc current and cannot radiate

RFI. There may also be a dc ground drop due to the difference

in currents returned on the analog and digital grounds. This will

not cause any problem. In fact, the AD650 will tolerate as much

as 0.25 volt dc potential difference between the analog and digi-

tal grounds. These features greatly ease power distribution and

ground management in large systems. Proper technique for

grounding requires separate digital and analog ground returns to

the power supply. Also, the signal ground must be referred di-

rectly to analog ground (Pin 11) at the package. All of the signal

grounds should be tied directly to Pin 11, especially the

one-shot capacitor. More information on proper grounding and

reduction of interference can be found in Reference 1.

TEMPERATURE COEFFICIENTS

The drift specifications of the AD650 do not include temperature

effects of any of the supporting resistors or capacitors. The drift

of the input resistors R1 and R3 and the timing capacitor COS

directly affect the overall temperature stability. In the application

of Figure 2, a 10 ppm/°C input resistor used with a 100 ppm/°C

capacitor may result in a maximum overall circuit gain drift of:

150 ppm/°C (AD650A) + 100 ppm/°C (COS) + 10 ppm/°C (RIN) 260 ppm/°C

and the drift of the offset voltage developed at the op amp non-

inverting input will be determined solely by the AD650. Under

these conditions the TC of the bipolar offset voltage is typically

–200 ppm/°C and is a maximum of –300 ppm/°C. The offset

voltage always decreases in magnitude as temperature is increased.

Other circuit components do not directly influence the accuracy

of the VFC over temperature changes as long as their actual val-

ues are not so different from the nominal value as to preclude

operation. This includes the integration capacitor, CINT. A

change in the capacitance value of CINT simply results in a dif-

ferent rate of voltage change across the capacitor. During the In-

tegration Phase (refer to Figure 2), the rate of voltage change

across CINT has the opposite effect that it does during the

Reset Phase. The result is that the conversion accuracy is un-

changed by either drift or tolerance of CINT. The net effect of a

change in the integrator capacitor is simply to change the peak

to peak amplitude of the sawtooth waveform at the output of the

integrator.

The gain temperature coefficient of the AD650 is not a constant

value. Rather the gain TC is a function of both the full-scale

frequency and the ambient temperature. At a low full-scale

frequency, the gain TC is determined primarily by the stability

of the internal reference—a buried Zener reference. This low

speed gain TC can be quite good; at 10 kHz full scale, the gain

TC near 25°C is typically 0 ± 50 ppm/°C. Although the gain

TC changes with ambient temperature (tending to be more

positive at higher temperatures), the drift remains within a

± 75 ppm/°C window over the entire military temperature range.

At full-scale frequencies higher than 10 kHz dynamic errors

become much more important than the static drift of the dc ref-

erence. At a full-scale frequency of 100 kHz and above, these

timing errors dominate the gain TC. For example, at 100 kHz

full-scale frequency (RIN = 40 k and COS = 330 pF) the gain TC

near room temperature is typically –80 ± 50 ppm/°C, but at an

ambient temperature near +125°C, the gain TC tends to be

more positive and is typically +15 ± 50 ppm/°C. This informa-

tion is presented in a graphical form in Figure 8. The gain TC

always tends to become more positive at higher temperatures.

Therefore, it is possible to adjust the gain TC of the AD650 by

using a one-shot capacitor with an appropriate TC to cancel the

drift of the circuit. For example, consider the 100 kHz full-scale

frequency. An average drift of –100 ppm/°C means that as

temperature is increased, the circuit will produce a lower fre-

quency in response to a given input voltage. This means that the

one-shot capacitor must decrease in value as temperature in-

creases in order to compensate the gain TC of the AD650; that

is, the capacitor must have a TC of –100 ppm/°C. Now consider

the 1 MHz full-scale frequency.

In bipolar configuration, the drift of the 1.24 kΩ resistor used to

activate the internal bipolar offset current source will directly af-

fect the value of this current. This resistor should be matched to

the resistor connected to the op amp noninverting input (Pin 2),

see Figure 4. That is, the temperature coefficients of these two

resistors should be equal. If this is the case, then the effects of

the temperature coefficients of the resistors cancel each other,

1“Noise Reduction Techniques in Electronic Systems,” by H. W. OTT,

(John Wiley, 1976).

REV. A

Figure 8. Gain TC vs. Temperature

–7–

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