ADM8690ARN-REEL Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Fabricante
ADM8690ARN-REEL Datasheet PDF : 24 Pages
| |||
Data Sheet
WATCHDOG OUTPUT (WDO) (ADM8691/ADM8695)
The watchdog output (WDO pin on the ADM8691/ADM8695)
provides a status output that goes low if the watchdog timer
times out and remains low until set high by the next transition
on the watchdog input. WDO is also set high when VCC goes
below the reset threshold.
8
OSC SEL
CLOCK
0 TO 500kHz
ADM8691/
ADM8695
7
OSC IN
Figure 17. External Clock Source
8
OSC SEL
COSC
ADM8691/
ADM8695
7 OSC IN
Figure 18. External Capacitor
8
NC
OSC SEL
ADM8691/
ADM8695
7
NC
OSC IN
Figure 19. Internal Oscillator (1.6 Second Watchdog)
8
NC
OSC SEL
ADM8691/
ADM8695
7
OSC IN
Figure 20. Internal Oscillator (100 ms Watchdog)
ADM8690/ADM8691/ADM8695
CE GATING AND RAM WRITE PROTECTION
(ADM8691/ADM8695)
The ADM8691/ADM8695 include memory protection circuitry
that ensures the integrity of data in memory by preventing write
operations when VCC is at an invalid level. Two additional pins
(CEIN and CEOUT) can be used to control the chip enable or write
inputs of CMOS RAM. When VCC is present, CEOUT is a buffered
replica of CEIN, with a 3 ns propagation delay. When VCC falls
below the reset voltage threshold or VBATT, an internal gate forces
CEOUT high, independent of CEIN.
CEOUT typically drives the CE, CS, or write input of battery
backed-up CMOS RAM. This ensures the integrity of the data
in memory by preventing write operations when VCC is at an
invalid level. Similar protection of EEPROMs can be achieved
using the CEOUT pin to drive the store or write inputs.
ADM8691/
ADM8695
CEIN
CEOUT
VCC LOW = 0
VCC OK = 1
Figure 21. Chip Enable Gating
VCC
V2
V1
V2
V1
RESET
t1
t1
LOW LINE
CEIN
CEOUT
t1 = RESET TIME
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2 – V1
Figure 22. Chip Enable Timing
Rev. C | Page 13 of 24
Share Link: 