CXD2492R Ver la hoja de datos (PDF) - Sony Semiconductor

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CXD2492R

Timing Generator for Frame Readout CCD Image Sensor

Sony Semiconductor 

Control data: D36 to D37 LDAD [ADCLK logic phase]

This indicates the ADCLK logic phase adjustment data. The default is 90° relative to MCKO.

D37 D36 Degree of adjustment (°)

0

0

0

0

1

90

1

0

180

1

1

270

CXD2492R

Control data: D38 to D39 STB [Standby]

The operating mode is switched as follows. However, the standby bits are loaded to the CXD2492R and

control is applied immediately at the rising edge of SEN.

D39 D38 Symbol

Operating mode

X

0 CAM Normal operating mode

0

1 SLP Sleep mode

1

1 STB Standby mode

See the Pin Status Table for the pin status in each mode.

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