CXD2463 Ver la hoja de datos (PDF) - Sony Semiconductor

Número de pieza

componentes Descripción

Fabricante

CXD2463

Timing Controller for CCD Camera

Sony Semiconductor 

CXD2463R

3) VReset + HPLL (VD and HD Inputs) Mode

When the HD cycle clock is externally input to EHD/SYNC (Pin 38) and the V cycle clock is externally input to

the EVD (Pin 37), the CXD2463R sync signal is output as shown below based on the phase difference

between these signals.

Similar to Line-Lock mode, the result of comparing the phase of the falling edges of the HD cycle clock input to

Pin 38 and the CXD2463R internal HD is output from COMP (Pin 39). The PLL is applied using this signal.

Similar to Line-Lock mode, the polarity of the COMP (Pin 39) output is compatible with the active filter. The

phase of the HD falling edge can be shifted up to ±1/4H with respect to the falling edge of the master VD (EXT-

VD).

• EIA/ODD

(1) EXT-VD and EXT-HD have the same phase.

1/4H 1/4H

EXT-VD

(Pin 37 input)

EXT-HD

(Pin 38 input)

VD

(Pin 35 output)

HD

(Pin 36 output)

SYNC

(Pin 25 output)

(2) EXT-VD and EXT-HD have the same phase to +1/4H.

EXT-VD

EXT-HD

VD

HD

SYNC

(3) EXT-VD and EXT-HD have the –1/4H to the same phase.

EXT-VD

EXT-HD

VD

HD

SYNC

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