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W83977ATF Datasheet PDF : 212 Pages
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W83977ATF
11.4 LOGICAL DEVICE 2 (UART A)¢) ................................................................................................................147
11.5 LOGICAL DEVICE 3 (UART B).................................................................................................................... 148
11.6 LOGICAL DEVICE 5 (KBC) .......................................................................................................................... 148
11.7 LOGICAL DEVICE 6 (IR) ..............................................................................................................................149
11.8 LOGICAL DEVICE 7 (GP I/O PORT I) ........................................................................................................... 151
11.9 LOGICAL DEVICE 8 (GP I/O PORT II)..........................................................................................................157
11.10 LOGICAL DEVICE 9 (GP I/O PORT III) ...................................................................................................... 163
11.11 LOGICAL DEVICE A (ACPI) ......................................................................................................................167
12.0 SPECIFICATIONS ..................................................................................................................................178
12.1 ABSOLUTE MAXIMUM RATINGS .................................................................................................................. 178
12.2 DC CHARACTERISTICS ......................................................................................................................... 178
12.3 AC CHARACTERISTICS ................................................................................................................................ 182
12.3.1 FDC: Data rate = 1 MB, 500 KB, 300 KB, 250 KB/sec......................................................................182
12.3.2 UART/Parallel Port.............................................................................................................................184
12.3.3 Parallel Port Mode Parameters ..........................................................................................................184
12.3.4 EPP Data or Address Read Cycle Timing Parameters ....................................................................... 185
12.3.5 EPP Data or Address Write Cycle Timing Parameters....................................................................... 186
12.3.6 Parallel Port FIFO Timing Parameters ..............................................................................................187
12.3.7 ECP Parallel Port Forward Timing Parameters ................................................................................187
12.3.8 ECP Parallel Port Reverse Timing Parameters .................................................................................. 187
12.3.9 KBC Timing Parameters ..................................................................................................................... 188
12.3.10 GPIO Timing Parameters.................................................................................................................. 189
13.0 TIMING WAVEFORMS......................................................................................................................... 190
13.1 FDC ............................................................................................................................................................190
13.2 UART/PARALLEL ....................................................................................................................................... 191
13.2.1 Modem Control Timing .......................................................................................................................192
13.3. PARALLEL PORT .........................................................................................................................................193
13.3.1 Parallel Port Timing............................................................................................................................193
13.3.2 EPP Data or Address Read Cycle (EPP Version 1.9).........................................................................194
13.3.3 EPP Data or Address Write Cycle (EPP Version 1.9) ........................................................................ 195
13.3.4 EPP Data or Address Read Cycle (EPP Version 1.7).........................................................................196
13.3.5 EPP Data or Address Write Cycle (EPP Version 1.7) ........................................................................ 197
13.3.6 Parallel Port FIFO Timing.................................................................................................................. 197
13.3.7 ECP Parallel Port Forward Timing ....................................................................................................198
13.3.8 ECP Parallel Port Reverse Timing...................................................................................................... 198
13.4 KBC............................................................................................................................................................199
13.4.1 Write Cycle Timing ..............................................................................................................................199
13.4.2 Read Cycle Timing............................................................................................................................... 199
13.4.3 Send Data to K/B ................................................................................................................................. 199
13.4.4 Receive Data from K/B ........................................................................................................................ 200
13.4.5 Input Clock ..........................................................................................................................................200
13.4.6 Send Data to Mouse.............................................................................................................................200
13.4.7 Receive Data from Mouse.................................................................................................................... 200
13.5 GPIO WRITE TIMING DIAGRAM.................................................................................................................. 201
13.6 MASTER RESET (MR) TIMING ..................................................................................................................... 201
14.0 APPLICATION CIRCUITS.................................................................................................................... 202
14.1 PARALLEL PORT EXTENSION FDD .............................................................................................................. 202
14.2 PARALLEL PORT EXTENSION 2FDD ............................................................................................................ 202
Publication Release Date: Apr 2001
-V-
Revision 0.53
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