Philips Semiconductors
5-band stereo equalizer circuit
PINNING
SYMBOL PIN
DESCRIPTION
ViL
F1LA
1 audio frequency input LEFT
2 connection A for filter 1 LEFT (f = 2.95 kHz)
n.c.
3 not connected
F1LB
4 connection B for filter 1 LEFT (f = 2.95 kHz)
F2LA
5 connection A for filter 2 LEFT (f = 12 kHz)
F2LB
6 connection B for filter 2 LEFT (f = 12 kHz)
F3LA
7 connection A for filter 3 LEFT (f = 790 Hz)
F3LB
8 connection B for filter 3 LEFT (f = 790 Hz)
F4LA
9 connection A for filter 4 LEFT (f = 205 Hz)
F4LB
10 connection B for filter 4 LEFT (f = 205 Hz)
F5LA
11 connection A for filter 5 LEFT (f = 59 Hz)
F5LB
12 connection B for filter 5 LEFT (f = 59 Hz)
VoL
VP
SDA
SCL
GND2
13 audio frequency output LEFT
14 supply voltage (+8.5 V)
15 I2C-bus data line
16 I2C-bus clock line
17 ground 2 (I2C-bus ground)
MAD
18 modul address
GND1
19 ground 1 (analog ground)
VoR
F5RB
20 audio frequency output RIGHT
21 connection B for filter 5 RIGHT (f = 59 Hz)
F5RA
22 connection A for filter 5 RIGHT (f = 59 Hz)
F4RB
23 connection B for filter 4 RIGHT (f = 205 Hz)
F4RA
24 connection A for filter 4 RIGHT (f = 205 Hz)
F3RB
25 connection B for filter 3 RIGHT (f = 790 Hz)
F3RA
26 connection A for filter 3 RIGHT (f = 790 Hz)
F2RB
27 connection B for filter 2 RIGHT (f = 12 kHz)
F2RA
28 connection A for filter 2 RIGHT (f = 12 kHz)
F1RB
29 connection B for filter 1 RIGHT (f = 2.95 kHz)
n.c.
30 not connected
F1RA
31 connection A for filter 1 RIGHT (f = 2.95 kHz)
ViR
32 audio frequency input RIGHT
Preliminary specification
TEA6360
Fig.2 Pin configuration
May 1991
4